Air gap, air gap forming method and semiconductor device

Abstract

The invention provides an air gap forming method which includes: firstly, a metal interconnection structure is provided, and the metal interconnection structure comprises metal structures and an intermetallic dielectric layer between the metal structures; photoetching and etching are performed on the intermetallic dielectric layer of the metal interconnection structure to form air gaps; the air gaps are sealed by a deposition interlayer dielectric layer; finally a conductive plug is manufactured on the interlayer dielectric layer; and the air gaps formed in the photoetching and etching step are of a plurality of D-shaped structures which are distributed in the shape of a honeycomb and have small top and bottom areas and a large middle area. The invention further provides the air gap structures and a semiconductor device with the structures. A top dielectric layer formed by the technical scheme is enhanced in mechanical strength, is not prone to collapse, and has low requirements on self-alignment accuracy when through holes are formed in a next process.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an air gap, a method for forming the air gap and a semiconductor device. Background technique [0002] When the semiconductor industry evolves the process technology below 90nm, the distance between adjacent connecting lines becomes smaller and smaller, and the capacitance generated between them becomes larger and larger. This capacitance is also called parasitic capacitance. This capacitance not only affects the operating speed of the chip , also has a serious impact on the reliability of the devices on the chip. In order to alleviate this problem, the semiconductor process replaces interlayer dielectric layers and intermetal dielectric layers with high dielectric constants such as silicon oxide (k=4.2) with low dielectric materials (3.0<k<4.2) to reduce the adjacent capacitance between the wires. When the process technology evolves to 32-45nm, the problem of c...

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Problems solved by technology

In addition, the method used to form the through holes in the layer 13 is self-alignment etching, and errors may occur during the self-alignment process, and offsets often occur, such as image 3 As shown in the cross-sectional view, the slight deviation will cause the formed via hole 15 to not completely fall on the metal structure, that is, partly formed in the air gap 14, which will cause voids (voids) to appear in the conductive plug formed later. ), the performance is unreliable, and in the case of severe offset, the conductive material that should have been filled in the through hole 15 will be filled into the air gap 14, resulting in undesired electrical conduction between the metal interconnection structures

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