Creating Anisotropic Diffused Junctions in Field Effect Transistor Devices

Abstract

A method for forming a transistor device comprising implanting a diffusion-inhibiting species in a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator layer having one or more gate structures formed thereon such that a diffusion inhibiting species is disposed in a portion of the semiconductor-on-insulator layer corresponding to the channel region, and in a portion of the buried insulator layer associated with the source and In the part corresponding to the drain region. Transistor dopant species are introduced in the source and drain regions. The anneal is performed to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

Description

technical field [0001] The present invention relates generally to the fabrication of semiconductor devices, and more particularly to creating anisotropically diffused junctions in field effect transistor (FET) devices. Background technique [0002] As the pitch between discrete devices on integrated circuits (ICs) continues to shrink with each new technology, the extent to which elements such as transistor gate electrodes and spacers and source and drain diffusion on these devices , the size needs to be reduced accordingly in both the horizontal and vertical directions. Accordingly, FET scaling has become a significant challenge in the semiconductor industry. Conventional scaling techniques such as shallow implantation and reduced thermal budget as device dimensions scale down to the nanometer (nm) scale (regime) because control over abrupt and shallow doping profiles is limited due to the inevitable transient-enhanced diffusion And start to stop working. A well-known met...

AI Technical Summary

Problems solved by technology

However, in sub-90nm technology nodes, where S / D stress-inducing elements such as epitaxially grown silicon germanium (eSiGe) and silicon carbide (eSiC) are incorporated for carrier mobility enhancement, the impact on S / D junction depth Scaling degrades device performance due to stress losses

In addition, shallow junctions lead to higher S / D series resistance, further degrading the performance of scaling devices

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