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Sense amplifier comparison circuit

A technology of sensitive amplifiers and comparison circuits, which is applied in the field of circuits, can solve problems such as limited applications, and achieve the effect of eliminating adverse effects

Active Publication Date: 2013-07-17
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] In the traditional structure above, the load transistors MP1 and MP2 are used as loads to generate voltage, and their source and drain will consume a large voltage margin to ensure that the comparison circuit has sufficient accuracy and speed, which limits its operation at low power supplies. Applications under voltage
With the advancement of technology, the used power supply voltage is gradually reduced, and it has dropped below 1.8V or even 1.5V. In this case, the sense amplifier comparison circuit with the above-mentioned traditional structure is no longer applicable.

Method used

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Examples

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Embodiment 1

[0057] Embodiment one, a kind of sense amplifier comparator circuit of reading, such as figure 2 As shown, it includes: a comparator, a memory unit circuit, a reference unit circuit, a first and a second clamping circuit;

[0058] a first current source generating circuit, the output end of which is connected to the first clamping circuit and the memory unit circuit;

[0059] A second current source generating circuit, the output end of which is connected to the second clamping circuit and the reference unit circuit;

[0060] a first current conversion voltage circuit connected between the ground and the first clamping circuit;

[0061] a second current conversion voltage circuit connected between the ground and the second clamping circuit;

[0062] One input terminal of the comparator is connected to the connection point between the first current conversion voltage circuit and the first clamping circuit, and the other input terminal is connected to the second current conve...

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PUM

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Abstract

The invention discloses a sense amplifier comparison circuit. The sense amplifier comparison circuit comprises a memory unit circuit, clamp circuits comprising first and second clamp circuits, and first and second current conversion voltage circuits; a first current source generation circuit, wherein the output end of the first current source generation circuit is connected with the first clamp unit and the memory unit circuit; and a second current source generation circuit, wherein the output end of the second current source generation circuit is connected with the second clamp circuit and a reference unit circuit; the fist current conversion voltage circuit is connected between ground and the first clamp circuit, and the second current conversion voltage circuit is connected between the ground and the second clamp circuit; and one input end of a comparator is connected with a connection point between the first current conversion voltage circuit and the first clamp circuit, and the other input end of the comparator is connected with a connection point between the second current conversion voltage circuit and the second clamp circuit. The sense amplifier comparison circuit can be used under a low power supply voltage condition.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a comparison circuit for a read sense amplifier. Background technique [0002] In the memory memory, data is stored in two forms of 1 and 0, corresponding to two basic memory units, the Erase cell and the Program cell, respectively. When reading memory data, in order to determine whether a certain memory cell is an Erase cell or a Program cell, it is necessary to compare the memory cell with a reference cell, which requires the use of a sense amplifier comparison circuit. [0003] The traditional sense amplifier structure is as follows figure 1 As shown, it includes: left and right circuits and a comparator; the comparator includes two input terminals and one output terminal. [0004] In the left half of the circuit, the floating gate MOS storage device Mcell represents a memory cell selected by the row decoding circuit and the column decoding circuit, its source is grounded, the contro...

Claims

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Application Information

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IPC IPC(8): G11C7/06
Inventor 丁冲刘铭范东风
Owner GIGADEVICE SEMICON (BEIJING) INC
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