Two-stage time digital convert (TDC) circuit

A time-to-digital conversion, two-stage technology, applied in the direction of analog/digital conversion, code conversion, electrical components, etc., can solve problems such as errors, achieve the effect of small circuit area, improve accuracy, and meet the measurement requirements of large range

Inactive Publication Date: 2013-07-17
SOUTHEAST UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This situation may cause errors at the moment of latching, and i

Method used

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  • Two-stage time digital convert (TDC) circuit
  • Two-stage time digital convert (TDC) circuit
  • Two-stage time digital convert (TDC) circuit

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Embodiment Construction

[0025] The present invention will be further described below in conjunction with the drawings and specific embodiments.

[0026] figure 1 It is the overall block diagram, the input signal of the circuit is the gate control signal EN, the stop pulse signal STOP, and the reset signal Reset, and the output signals are: Q1, Q2, ... Qi, where i is the number of output signals. The circuit works when the gate control signal EN is high level, and the circuit stops working when it is low level. The rising edge of stop pulse signal STOP is valid. When the stop pulse signal STOP is valid, the TDC stops counting, and the circuit outputs the counting result.

[0027] figure 2 It is the overall structure diagram of the circuit. The circuit is mainly composed of a fine counter part (the first counter part) and a coarse counter part (the second counter part). The fine counter part includes a delay unit, a decoding circuit, a buffer stage, a latch, and a delay unit The circular delay lin...

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PUM

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Abstract

The invention discloses a two-stage TDC circuit. The two-stage TDC circuit comprises a first counter portion and a second counter portion, wherein the first counter portion comprises a delay unit, a decoding circuit and a latch, a closed-loop delay line type structure is adopted, and the second counter portion is a pseudo random sequence counter. The two-stage TDC circuit is controlled by gating signals, capable of being turned on and off repeatedly, determined in the initial state and rapid in start. The circuit is applied to an array type infrared three-dimensional imaging reading circuit and configured outside, inside or partially outside pixels as required. Compared with an ordinary TDC circuit, the circuit is simple in structure and capable of working at high frequency, improving the temporal resolution, generating stable oscillation frequency simultaneously and satisfying application requirements for small pixel circuit area, low power consumption and high temporal resolution in array type infrared imaging reading circuits.

Description

technical field [0001] The invention relates to a time-to-digital conversion circuit, which is used in an array type infrared sensing readout circuit. Background technique [0002] TDC (Time Digital Convert, time-to-digital conversion circuit) is the basic means of time measurement. This technology has an important position and is widely used in the fields of aerospace, ranging, metrology, and measurement. The traditional TDC circuit implemented based on analog technology has exposed its shortcomings such as unstable operation, susceptibility to external noise, temperature and voltage interference, etc., resulting in large errors in its measurement results, and is not suitable for large-scale and high-precision measurement, which limits this development of a technology. With the rapid development of digital integrated circuit technology and CMOS technology, the TDC circuit realized by digital technology has the advantages of simple process, low cost, good portability, stabl...

Claims

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Application Information

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IPC IPC(8): H03M1/50
Inventor 郑丽霞吴金杨俊浩董怀朋孙伟锋宋慧滨高新江孙力军张秀川蒋利群
Owner SOUTHEAST UNIV
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