Dual-port peripheral configuration interface circuit

A configuration interface, dual-port technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of resource waste, cumbersome, hardware resource waste, etc., and achieve the effect of convenient rate adjustment, simple communication protocol, and simple circuit

Inactive Publication Date: 2013-07-31
BEIJING UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] There are many commonly used peripheral configuration interface circuits, but in the application of a single master to a single slave, it is often cumbersome. For example, the commonly used SPI (Serial Peripheral Interface) interface requires 4 CSN/SCK/MOSI/MISO. Ports, MOSI/MISO will not work at the same time, resulting in waste of resources; and the commonly used I2C (Inter-Integrated Circuit) interface, although there are only two ports used, SCL/SDA, but in terms of speed, only 100Kps/400Kbps /3.4Mbps The rate

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[0019] The dual-port peripheral configuration interface circuit described in the present invention can use a unified dual port to communicate with the outside when connecting different peripherals, and the communication rate is completely determined by the external clock.

[0020] The specific embodiments of the present invention are given below in conjunction with the drawings.

[0021] figure 1 It is the electrical schematic diagram of the interface circuit of the present invention, mainly composed of clock counter p_cnt[3:0], read and write judgment register p_r_wn, address / data shift register p_d_shift[7:0], read data shift register n_d_shift[7:0 ], address register p_reg_addr[6:0], write enable signal generation register n_reg_wr, ​​read enable signal generation register n_reg_rd.

[0022] After the verification of the interface circuit design of this embodiment is completed, the RTL (Register Transfer Level) code is synthesized to form a netlist, and the layout is drawn corresp...

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Abstract

The invention belongs to the field of embedded systems, and discloses a dual-port peripheral configuration interface circuit. According to the interface circuit, only two IO interfaces are provided externally, one is an RCK (read clock) input port, and the other is an RDA (remote data access) data two-way port. A read-write data port, a read/write address signal port, and a read-write enable signal port are connected with a register set. The interface circuit comprises a clock counter, a read-write judging register, an address/data shifting register, a read data shifting register, an address register, a write enable signal generation register and a read enable signal generation register. The interface circuit disclosed by the invention has the advantages that the communication protocol and the circuit are simple, external ports are few, the communication speed changes with the rate change of an externally supplied RCK clock, an externally supplied system clock is not needed, and the like.

Description

technical field [0001] The invention belongs to the field of embedded systems and relates to an all-digital logic dual-port peripheral configuration interface circuit. Background technique [0002] There are many commonly used peripheral configuration interface circuits, but in the application of a single master to a single slave, it is often cumbersome. For example, the commonly used SPI (Serial Peripheral Interface) interface requires 4 CSN / SCK / MOSI / MISO. Ports, MOSI / MISO will not work at the same time, resulting in waste of resources; and the commonly used I2C (Inter-Integrated Circuit) interface, although there are only two ports used, SCL / SDA, but in terms of speed, only 100Kps / 400Kbps / 3.4Mbps These three kinds of protocols stipulate the good rate. And according to the agreement, the slave needs to respond ACK every time after the master sends data, which is unnecessary for single-master and single-slave systems, resulting in a waste of hardware resources; and another...

Claims

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Application Information

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IPC IPC(8): G06F13/28
Inventor 乔龙林平分万培元裘武龙黄廷昭
Owner BEIJING UNIV OF TECH
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