Decoupling capacitor and integrated circuit provided with same

Abstract

The application provides a decoupling capacitor, which comprises a decoupling capacitor body and resistor connected with a gate electrode of an MOS transistor, wherein the decoupling capacitor body adopts the MOS transistor. The application further provides a integrated circuit, which comprises the decoupling capacitor comprising an NMOS transistor and a PMOS transistor, wherein a drain of the PMOS transistor is connected onto a gate electrode of the NMOS; a drain of the NMOS transistor is connected onto a gate electrode of the PMOS transistor; and the source voltage of the PMOS transistor is higher than that of the NMOS transistor. The decoupling capacitor and the integrated circuit provided with the decoupling capacitor can increase the ESD protection capability.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a decoupling capacitor and an integrated circuit with the decoupling capacitor. Background technique [0002] With the reduction of integrated circuit process geometry, more and more transistors are integrated on a chip, and the clock frequency has been expanded to the range of GHz, the density and speed performance of integrated circuit chips have been significantly improved, making these The switching time of the system composed of devices reaches sub-nanoseconds. However, this high-speed switching process often results in high transient currents, supply voltage variations that cause power supply chatter. At the same time, in order to reduce power consumption, the power supply voltage has been reduced along with the reduction of process size, so integrated circuits will be more and more susceptible to power supply noise. [0003] For this reason, it is c...

AI Technical Summary

Problems solved by technology

Because the gate oxide of the NMOS transistor is very thin, it can provide a large capacitance, but it is precisely because the gate oxide of the NMOS transistor is very thin that the electrostatic discharge (ESD, Electro-Static discharge) protection capability is reduced, that is, the potential electrostatic discharge risk of breaking down the gate oxide, permanently destroying the chip

With the continuous reduction of process size, especially starting from 90nm process, the gate oxide is getting thinner and thinner. This traditional decoupling capacitor structure is facing more and more ESD risks.

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