Semiconductor memory and manufacturing method thereof

Abstract

The invention discloses a semiconductor memory which is a memory unit in a not or (NOR) type flash-memory memory array. The semiconductor memory comprises a substrate, a tunneling layer, a floating gate, a control gate and a barrier layer, wherein the tunneling layer is arranged on the substrate, the floating gate and the control gate are arranged on the tunneling layer, and the barrier layer is arranged between the floating gate and the control gate. The floating gate is made of monocrystal semiconductor materials or microcrystal semiconductor materials. The monocrystal or the microcrystal is of a compact structure, spreading of doping objects in the polycrystalline silicon floating gate through crystal particle gaps is effectively avoided, performance and reliability of the memory are improved, the even and high-quality barrier layer can be easily formed on the monocrystal or microcrystal floating gate, and the reliability of the memory is further improved.

Description

technical field [0001] The present invention relates to semiconductor and manufacturing technology, more specifically, to a semiconductor memory and its manufacturing method. Background technique [0002] With the popularity of portable personal devices, the demand for memory has further increased, and the research on memory technology has become an important direction of information technology research. In order to better improve the storage density and the reliability of data storage, the research and development focus is gradually concentrated in non-volatile memory. NOR flash memory is a commonly used non-volatile memory with high-speed characteristics. It is usually used in mobile phones and communication chips as code storage. [0003] The usual NOR flash memory is mostly polysilicon floating gate structure, such as figure 1 and figure 2 as shown, figure 1 It is a schematic layout diagram of a storage array of a conventional NOR type floating gate flash memory, ...

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Problems solved by technology

As the device is scaled down, the interval between memory cells is getting smaller and smaller. In order to ensure a high coupling coefficient from the control gate to the floating gate, and due to the large thickness of the barrier layer of the three-layer IPD structure, in order to ensure a high coupling coefficient and device performance, the spacing w between cells is difficult to reduce, which limits the further reduction of device cells and affects the improvement of storage density

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