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MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory)

A controller and standard technology, applied in the direction of instruments, static memory, etc., can solve problems such as unfavorable promotion and development of MBIST technology, reducing test costs, disadvantages, etc.

Inactive Publication Date: 2013-09-18
GUILIN UNIV OF ELECTRONIC TECH
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Problems solved by technology

[0002] The built-in self-test (BIST) method is generally used for testing embedded memories. This method can realize fault detection for embedded memories, but the existing methods can only detect faults for the same type of embedded memories and cannot be used. A MBIST (memory built-in self-test) controller to complete the test of many different kinds of embedded memories
[0003] Generally, the same SoC chip contains multiple different types of embedded memories. If a corresponding MBIST controller is designed for each type of memory, the hardware consumption of the MBIST system of the entire SoC chip will be very large, which is not conducive to Reducing the cost of testing is also not conducive to the promotion and development of MBIST technology

Method used

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  • MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory)
  • MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory)
  • MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory)

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Embodiment Construction

[0064] The specific embodiments of the present invention will be described in detail below with reference to the drawings and embodiments.

[0065] see figure 1 . The MBIST controller with the March algorithm state machine and the multi-input linear feedback shift register MISR are respectively connected to the peripheral test system interface, the test shell wrapper and response analysis based on the IEEE 1500 standard surrounding the tested embedded SRAM and ROM core The test shell Wrapper based on the IEEE 1500 standard is connected with the response analyzer. The test shell Wrapper and the response analyzer based on the IEEE 1500 standard are both embedded in the system chip.

[0066] see figure 2 . In the MBIST controller, the March algorithm state machine is followed by the instruction decoder and the control signal generator. After the instruction decoder, the data background generator, address generator and read-write signal generator, data background generator, address ...

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Abstract

The invention discloses a testing structure and a testing method based on an IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with an SRAM / ROM (Static Random Access Memory / Read Only Memory) test. A testing structure is combined with a method of embedded type core testing standard IEEE1500 and a BIST; the testing structure supports to carry out the BIST on a plurality of embedded type SRAMs and ROMs with different types. The structure is formed by two parts, including a testing shell package of the embedded type SRAM and the ROM and an MBIST controller. The testing shell package solves the control problems of testing access, testing isolation and testing of the embedded type SRAM and the ROM. The MBIST controller generates testing stimulation data needed by an SRAM test according to a testing algorithm, controls a package shell Wrapper, carries out response analysis and outputs a testing result; an MISR (Multiple Input Shift Register) is used for finishing data compression operation on data in the ROM. With the adoption of the testing structure and the testing method, the faults of the embedded type SRAM and the ROM can be detected, so as to be good for test reuse of the embedded type SRAM and the ROM; the integration efficiency of an SoC (System on Chip) is effectively improved and the consumption of hardware of an MBIST system is also reduced.

Description

Technical field [0001] The invention relates to a SoC chip, in particular to the embedded memory in the SoC chip, and more specifically to the testing of the embedded memory in the SoC chip. Background technique [0002] The test of embedded memory generally adopts the built-in self-test (BIST) method, which can realize the fault detection of embedded memory, but the existing methods can only perform fault detection on the same type of embedded memory, and cannot be used An MBIST (Memory Built-in Self-Test) controller is used to test multiple different types of embedded memories. [0003] Generally, the same SoC chip contains multiple different types of embedded memories. If a corresponding MBIST controller is designed for each type of memory, the hardware consumption of the MBIST system of the entire SoC chip will be very large, which is not conducive to Reducing test costs is also not conducive to the promotion and development of MBIST technology. Summary of the invention [000...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56
Inventor 谈恩民金锋
Owner GUILIN UNIV OF ELECTRONIC TECH
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