Chip stack structure and method for fabricating the same

Abstract

A chip stack structure taking a wafer as a stacking base and stacking chips thereon is provided. The chip stack structure is capable of achieving high density electrode bonding and breaking the bottleneck of requiring interposer to serve as a transferring interface in three dimensional chip package. The chip stack structure is easily fabricated and compatible with wafer level process, so as to reduce processing time and manufacturing cost. A method for fabricating the chip stack structure is also provided.

Description

technical field [0001] The invention relates to a semiconductor technology, in particular to a chip stacking structure and a manufacturing method thereof. Background technique [0002] In today's information society, the design of electronic products is developing towards the trend of light, thin, short and small. The use of three-dimensional chip integration technology can realize high-density chip construction, and has the advantages of high efficiency and low energy consumption. For example, in the field of portable electronic products that emphasize multi-function and small size, including Solid State Disk / Drive (SSD) or Dynamic Random Access Memory (DRAM), etc., in addition to enhancing high-speed performance, it can also be used in With the same number of I / Os, the power loss required for chip operation is reduced, and at the same time, the requirements for capacity, performance and I / O improvement are met. [0003] The stacking process used in the current 3D chip in...

AI Technical Summary

Problems solved by technology

For example: the temperature of the joining process is higher, which may cause higher structural residual stress

When performing high-density chip packaging, due to the narrow cutting line, it is not conducive to the subsequent dispensing process

In addition, the module still needs to be molded after the dispensing of glue, but because the existing chip stacking is to temporarily attach the large wafer to the carrier through the glue material, and then stack the chips on the large wafer, Therefore, when the molding is completed and debonding is performed, some adhesive material will remain on the bumps, affecting the processing yield

In addition, the bonding interface between the packaging module and the external intermediary substrate or circuit substrate is easily damaged, which affects the reliability of the overall product

Images