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Storage controller integrating addressing function and storage unit

A technology of storage controller and storage unit, which is applied in the field of operation control circuit and timing control, and can solve the problems of increasing the burden of microprocessor execution program instruction flow, unfavorable execution instruction sequence speed, single function, etc.

Active Publication Date: 2013-10-02
GUANGXI UNIVERSITY OF TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Memory is a must-have component for microcomputer systems and various intelligent systems, whether it is the memory embedded in the microprocessor chip in these systems, or the externally expanded memory connected to the microprocessor through the system bus, including the internal memory of the microprocessor. Register groups, etc., all have the function of reading and writing operations, but the function is single, that is, according to the address value of the internal address bus of the microprocessor or the address value of the external system address bus, the register or storage unit of the address is directly read and written.
The addressing process of these memories and registers is completed by the microprocessor. For other more complex addressing methods such as indirect addressing, base address plus index addressing, it also involves address calculation, address data transmission and other processes; On the other hand, the data transmission between the storage units in the memory generally needs to be transferred through a certain register inside the microprocessor to realize the data transmission between the storage units, that is, two transfer instructions are required to complete the data transmission in the memory. The data of a certain storage unit of the storage unit is transferred to another storage unit; the addressing process of the memory and the register, and the process of data transmission between the storage units in the memory will cost the clock cycle of the microprocessor, increasing the microprocessor The burden of executing the program's instruction stream is not conducive to improving the speed of executing instruction sequences

Method used

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  • Storage controller integrating addressing function and storage unit
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  • Storage controller integrating addressing function and storage unit

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Embodiment Construction

[0111] An addressing function integrated memory controller with memory cells, such as figure 1 As shown, the integrated storage controller includes a command register and address temporary storage control module I, a storage unit II, a combinational logic circuit module III, a pulse distributor IV, a data transmission control module V and an address channel control module VI;

[0112] The command storage and address temporary storage control module I are respectively connected with the storage unit II, the combinational logic circuit module III, the pulse distributor IV, the data transmission control module V and the address channel control module VI;

[0113] The storage unit II is also connected to the data transmission control module V and the address channel control module VI;

[0114] The combined logic circuit module III is also connected with the pulse distributor IV, the data transmission control module V and the address channel control module VI;

[0115] The pulse ...

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Abstract

The invention discloses a storage controller integrating the addressing function and a storage unit. The storage controller integrating the addressing function and the storage unit comprises an order registering and address temporary-storage control module, the storage unit, a combinational logical circuit module, a pulse distributor, a data transmission control module and an address channel control module, wherein an FPGA is applied to the storage controller and used for designing a hard connection control circuit, so that the storage controller has the access function of a common storage device, and when the storage controller executes an order of data writing or an order of data transmitting between two storage units, CS is changed into '0' from '1' after order parameters are written into the order registering and address temporary-storage control module. Under the action of internal timing pulses, parallel operation of the process of addressing, data transmitting and writing of the kind of orders and the process that a microprocessor executes other order sequences is achieved. When the storage controller integrating the addressing function and the storage unit executes a data reading order, addressing of the storage unit is finished by the storage controller by itself, a system sends a reading signal according to the timing sequence requirement, data of the storage unit are sent to a data bus of the system, and therefore the parallel processing function of the FPGA is fully applied.

Description

technical field [0001] The present invention relates to an integrated storage controller with addressing function and storage unit, in particular to an operation control circuit and timing control of an integrated storage controller with addressing function and storage unit based on FPGA parallel operation circuit hard connection. Background technique [0002] Memory is a must-have component for microcomputer systems and various intelligent systems, whether it is the memory embedded in the microprocessor chip in these systems, or the externally expanded memory connected to the microprocessor through the system bus, including the internal memory of the microprocessor. The register group and so on all have read and write operation functions, but the function is single, that is, according to the address value of the internal address bus of the microprocessor or the address value of the external system address bus, the register or storage unit of the address is directly read and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16
Inventor 李克俭蔡启仲余玲潘绍明周曙光黄仕林孙培燕
Owner GUANGXI UNIVERSITY OF TECHNOLOGY
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