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Method and apparatus for non-volatile memory unit

A technology of non-volatile storage and storage unit, which is applied in the field of non-volatile storage unit structure, and can solve problems such as difficulty in reliable operation

Active Publication Date: 2017-07-04
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

These changes make it difficult to operate reliably

Method used

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  • Method and apparatus for non-volatile memory unit
  • Method and apparatus for non-volatile memory unit
  • Method and apparatus for non-volatile memory unit

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Embodiment Construction

[0038] The making and using of the preferred embodiment are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific examples discussed are merely illustrative of specific ways to make and use the embodiments, and do not limit the scope of the embodiments or the appended claims.

[0039] figure 1 A cross-sectional view of a typical MOS transistor type Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) cell 11 is shown as a non-limiting example. In this example, cell 11 uses sidewall storage. Gate electrode 13 is formed over gate dielectric layer 15 formed over semiconductor substrate 20 . The semiconductor substrate may be formed from bulk silicon, gallium arsenide, germanium, silicon germanium, or other semiconductor materials used in integrated circuits. Source / drain regions 17 are shown on either side of the channel region 19 in ...

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Abstract

Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source / drain terminal of the first and the second storage cell and coupled to a second source / drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data.

Description

technical field [0001] The present invention relates to non-volatile memory cell structures and methods for providing non-volatile memory cell structures for embedded logic circuits and compatible with advanced semiconductor manufacturing processes. Background technique [0002] A current general requirement for electronic circuits, and especially for electronic circuits that are fabricated as integrated circuits in semiconductor processes, is an array of memory storage elements. These elements may be configured as non-volatile memory (NVM) cells. In the traditional NVM structure, FLASH memory can be used. However, for example, the use of FLASH memory requires semiconductor process steps in addition to advanced semiconductor processes for logic circuits. FLASH cells require expensive process steps. More recently, logic-compatible NVM cells have been developed. Some of these logic compatible memory cells use floating gates, where the floating gates are formed using logic ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/02G11C16/06
CPCG11C16/0458G11C11/5621H01L29/42348H01L29/7923
Inventor 池育德
Owner TAIWAN SEMICON MFG CO LTD