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Power MOS device structure

A MOS device and power technology, used in semiconductor devices, electrical solid state devices, semiconductor/solid state device components, etc., can solve the problem of high cost, relieve stress, reduce on-resistance, and increase the number of effects

Inactive Publication Date: 2013-11-13
CSMC TECH FAB1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to further reduce the on-resistance, it is necessary to increase the number of LDMOS basic units. Since the existing method does not place devices under the Bonding PAD, the more the number of LDMOS basic units, the larger the chip area occupied by the device, so the cost will be higher.

Method used

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Embodiment Construction

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0024] As mentioned in the background art section, in the design of existing power MOS devices, considering the high stress during packaging and wiring, it is easy to damage the devices under the solder pads. Usually, devices are not placed under the solder pads, but the chip area is sacrificed to increase the basic LDMOS. The number of units to achieve the goal of reducing on-resistance. However, the power MOS device manufactured by this method...

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PUM

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Abstract

The invention discloses a power MOS device structure which comprises a plurality of LDMOS elementary units and a plurality of welding gaskets. The LDMOS elementary units are connected in parallel, and are electrically connected with the welding gaskets through metal to lead out the gate terminals, the source terminals, the drain terminals and the substrates of the LDMOS elementary units. The LDMOS elementary units are arranged under the welding gaskets. The welding gaskets comprise single-layer metal with the thickness ranging from 3.5 microns to 4.5 microns and the line width ranging from 1.5 microns to 2.5 microns. The area of a chip below the welding gaskets of a power MOS device is fully utilized, the number of the LDMOS elementary units which are connected in parallel is increased under the premise that the total area of the chip is not increased, and therefore the on resistance can be effectively reduced.

Description

Technical field [0001] The invention relates to a power MOS (Power Metal-Oxide-Semiconductor Field-Effect Transistor) device structure, in particular to a power MOS device structure with low on-resistance, and belongs to the field of semiconductor device manufacturing. Background technique [0002] The drain-source on-resistance of a power MOS device determines its application power. When the on-resistance is very small, the device will provide a good switching characteristic, and there will be a larger output current, which can have a stronger Drive capability. Reducing the on-resistance as much as possible is the goal pursued by power MOS devices. [0003] From the calculation formula of on-resistance It can be obtained that the larger the channel width W, the lower the on-resistance R. Therefore, the power MOS device can use multiple LDMOS (Lateral Double-diffused MOS) basic units in parallel to increase the total channel width and reduce the on-resistance. [0004] Existing p...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/49
CPCH01L23/482H01L24/06H01L29/7816H01L23/4824H01L23/485H01L29/78H01L24/05H01L2924/13091H01L2924/1306H01L29/7835H01L2924/00H01L24/08H01L24/09H01L24/07H01L24/02
Inventor 章舒何延强罗泽煌吴孝嘉
Owner CSMC TECH FAB1