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Packaging-prior-to-etching chip-normally-bonded bump type three-dimensional system-level metal circuit board and process method thereof

A technology of etching first and then sealing metal lines, which is applied to circuits, semiconductor/solid-state device parts, semiconductor devices, etc., and can solve the problems of limiting the functionality and application performance of metal lead frames

Active Publication Date: 2013-11-20
江阴芯智联电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] The purpose of the present invention is to overcome the above-mentioned disadvantages, and provide a three-dimensional system-level metal circuit board and a process method for etching first and then sealing the chip. application performance

Method used

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  • Packaging-prior-to-etching chip-normally-bonded bump type three-dimensional system-level metal circuit board and process method thereof
  • Packaging-prior-to-etching chip-normally-bonded bump type three-dimensional system-level metal circuit board and process method thereof
  • Packaging-prior-to-etching chip-normally-bonded bump type three-dimensional system-level metal circuit board and process method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0209] Embodiment 1, single-layer line single-chip front-mounted single-turn pins

[0210] see Figure 27 , which is a structural schematic diagram of Embodiment 1 of a three-dimensional system-level metal circuit board with bumps mounted on chips and then sealed in the present invention, which includes a metal substrate frame 1, and base islands 2 and pins 3 are arranged in the metal substrate frame 1, The front of the base island 2 is provided with a chip 5 through a conductive or non-conductive adhesive substance 4, the front of the chip 5 is connected with the front of the pin 3 by a metal wire 6, and a conductive pillar is arranged on the front of the pin 3 7. The area around the base island 2, the area between the base island 2 and the pin 3, the area between the pin 3 and the pin 3, the area above the base island 2 and the pin 3, the base island 2 and the The area under the pin 3, the chip 5, the metal wire 6 and the conductive pillar 7 are all encapsulated with a plas...

Embodiment 2

[0264] Embodiment 2, multi-turn single-chip formal installation + passive components + electrostatic discharge ring

[0265] see Figure 28 , which is a structural schematic diagram of Embodiment 2 of the three-dimensional system-level metal circuit board with bumps mounted on the chip and then sealed in the present invention. The difference between Embodiment 2 and Embodiment 1 lies in that the conductive pillar 7 has multiple turns, and the lead Between the pin 3 and the pin 3, the passive device 10 is bridged by a conductive adhesive substance, and an electrostatic discharge ring 11 is arranged between the base island 2 and the pin 3, and the front side of the electrostatic discharge ring 11 is connected to the front side of the chip 5 The passive device 10 can be connected between the front of the pin 3 and the front of the pin 3, or between the front of the pin 3 and the front of the electrostatic discharge ring 11, or across It is connected between the front of the base...

Embodiment 3

[0266] Embodiment 3, single-circle multi-base island tiling multi-chip formal installation

[0267] see Figure 29 , which is a structural schematic diagram of Embodiment 3 of the three-dimensional system-level metal circuit board with bumps mounted on the chip before sealing the chip according to the present invention. The difference between Embodiment 3 and Embodiment 1 is that there are multiple base islands 2. Chips 5 are provided on the base island 2 through conductive or non-conductive adhesive substances 4 , and the fronts of the chips 5 are connected with the fronts of the chips 5 through metal wires 6 .

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Abstract

The invention relates to a packaging-prior-to-etching chip-normally-bonded bump type three-dimensional system-level metal circuit board and a process method thereof. The metal circuit board structurally comprises a metal substrate frame, wherein a pad and pins are arranged in the metal substrate frame; chips are arranged on the front surface of the pad; the front surfaces of the chips and the pins are connected through metal wires; conductive columns are arranged on the front surfaces of the pins; molding compounds are encapsulated in the peripheral area of the pad, the areas between the pad and the pins and between each two pins, the upper areas of the pad and the pins, the lower areas of the pad and the pins, and the external areas of the chips, the metal wires and the conductive columns; anti-oxidation layers are plated on the surfaces, exposed from the molding compounds, of the metal substrate frame, the pins and the conductive columns; and metal balls are arranged on the tops of the conductive columns. By virtue of the packaging-prior-to-etching chip-normally-bonded bump type three-dimensional system-level metal circuit board and the process method thereof, the problem of limitation of the functionality and application performance of a metal lead frame caused by difficulty in embedding of an object into a conventional metal lead frame can be solved.

Description

technical field [0001] The invention relates to a three-dimensional system-level metal circuit board with bumps mounted on chips and a process method thereof after etching first and then sealing chips. It belongs to the technical field of semiconductor packaging. Background technique [0002] The basic manufacturing process methods of traditional metal lead frames are as follows: [0003] 1) Take a metal sheet and use the technology of mechanical upper and lower tool punching to make punching from top to bottom or bottom to top in a longitudinal manner, so that the lead frame can form a base island carrying a chip and signal transmission in the metal sheet The inner pins used are connected to the outer pins of the external PCB, and then some areas of the inner pins and (or) the base island are covered with metal plating to form a lead frame that can actually be used (see Figure 78~Figure 80 ). [0004] 2) Take a metal sheet and use chemical etching technology for exposure...

Claims

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Application Information

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IPC IPC(8): H01L21/48H01L21/56H01L23/495H01L23/31
CPCH01L2924/19107H01L2224/32145H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/48091H01L2224/73265H01L2924/00014
Inventor 张凯张友海廖小景王亚琴王孙艳
Owner 江阴芯智联电子科技有限公司
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