Trimming resistance control device and wafer test system using the same
A technology for trimming and adjusting resistors and control devices, which is applied in the direction of single semiconductor device testing, circuits, electrical components, etc., can solve the problems of simultaneous fusing of multiple fuses, high cost of wafer testing, and long wafer testing time, etc., to achieve Effect of Shortening Wafer Test Time
Active Publication Date: 2016-05-04
WUXI ZGMICRO ELECTRONICS CO LTD
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Problems solved by technology
The trimming resistance control device 120 cannot fuse multiple fuses at the same time. The reason is that each fuse requires a certain voltage (for example, 5V, that is, the voltage values of the constant voltage sources V1-V4 are all 5V). When fusing at the same time, constant voltage sources V1 to V4 are required to fully charge capacitors C1 to C4 first, and then capacitors C1 to C4 are connected to the pressure points of A, B, C, D, and E probes at the same time. The voltage of points A and E will reach 20V, and the highest safe voltage for low-voltage chips is 6V, and it may be damaged by overvoltage
[0007] Since the trimming resistor control device 120 in the prior art can only blow the fuses in the trimming resistor 110 one by one, it takes a long time for wafer testing, and the testing cost is proportional to the testing time, resulting in higher wafer testing costs , therefore, it is necessary to provide an improved technical solution to overcome the above problems
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[0020] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0021] Reference herein to "one embodiment" or "an embodiment" refers to a particular feature, structure or characteristic that can be included in at least one implementation of the present invention. "In one embodiment" appearing in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words connected, connected, and joined in this document mean that they are electrically connected directly or indirectly.
[0022] Please refer to figure 2 As shown, it is a schematic circuit diagram of a wafer testing system in an embodiment of the present invention. figure 2 The mid-wafer ...
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The present invention provides a trimming resistance control device and a wafer testing system using the device. The trimming resistance control device includes: a plurality of voltage sources connected in sequence, and two adjacent voltage sources are separated by respective The same electrodes are connected; multiple capacitors are connected in series, each capacitor is connected in parallel with its corresponding voltage source; multiple trim switches and multiple probes; the middle node of each two connected capacitors is connected to a trim switch through a trim switch The probes are connected, and the connection end of the outermost capacitor that is not connected to other capacitors is connected to a probe through a trim switch. Compared with the prior art, the trimming resistance control device and the wafer testing system using the device in the present invention include N voltage sources connected in sequence, and two adjacent voltage sources are connected through the same electrode. This allows multiple fuses in the trimming resistor to be blown at the same time, thereby shortening wafer testing time.
Description
【Technical field】 [0001] The invention relates to the field of wafer testing, in particular to a trimming resistance control device and a wafer testing system using the device. 【Background technique】 [0002] Wafer testing usually consists of a test machine and a probe card to build a test environment, in which the chips on the wafer are tested to ensure that the electrical characteristics and functions of each chip meet the design specifications and specifications. Wafers that fail the test will be marked as bad products or bad chips, and will be rejected in the subsequent dicing and packaging stage, and only the wafers that pass the test will be packaged as chips. In the wafer testing stage, in order to improve the yield and quality of the wafer, it is usually necessary to perform necessary trimming and programming on several parameters of the wafer, so as to achieve higher performance or differentiated functions. [0003] A wafer testing method in the prior art is as fol...
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IPC IPC(8): H01L23/525H01L21/67G01R31/26
Inventor 王钊
Owner WUXI ZGMICRO ELECTRONICS CO LTD