Grid voltage bootstrapping switch circuit

Abstract

The invention relates to an integrated circuit technique, and provides a grid voltage bootstrapping switch circuit by solving the problems that the circuit of the existing grid voltage bootstrapping switch circuit occupies greater area, and in addition, the capacitive load of the input end is also greater. The grid voltage bootstrapping switch circuit has the technical scheme that the grid voltage bootstrapping switch circuit is characterized by comprising a grid voltage boosting circuit, a grid electrode charge and discharge circuit, an input buffer circuit and a switch circuit, wherein the grid voltage boosting circuit is connected with the grid electrode charge and discharge circuit, the input buffer circuit is connected with the grid voltage boosting circuit, and the grid electrode charge and discharge circuit is connected with the switch circuit. The grid voltage bootstrapping switch circuit has the beneficial effects that the occupied area of the circuit is greatly reduced, the input parasitic capacitance is reduced, and the grid voltage bootstrapping switch circuit provided by the invention is applicable to grid voltage bootstrapping switch circuits.

Description

technical field [0001] The invention relates to integrated circuit technology, in particular to a gate voltage bootstrap switch circuit. Background technique [0002] With the development of technology, high speed and high precision have become the design goals of analog-to-digital converters. Pipelined ADC, as one of the current mainstream ADC products, can meet the requirements of speed and precision well. In the pipeline analog-to-digital converter, the digital-to-analog converter (MDAC) with multiplication is an important part, and its performance determines the performance of the entire pipeline analog-to-digital converter. As the process size shrinks, the switching circuit used in the digital-to-analog converter with multiplication will undoubtedly face new challenges. There are more and more researches on the switching voltage in the sample and save circuit, and the requirements are high linearity and high speed; for the switching circuit in the digital-to-analog co...

AI Technical Summary

Problems solved by technology

[0007] However, it can be seen that in the working state (1), in order to turn on the fourth NMOS transistor MN4, a charge pump structure with a capacitor is used to raise the voltage of the second node N2 to 2X, so that the additional capacitor will be Will take up a lot of area, especially for nanoscale processes

In addition, in the working state (2), when the eighth NMOS transistor MN8 is turned on, the input is equivalent to being directly connected to the lower plate of the third capacitor C3, plus the eleventh NMOS transistor MN11, the fourth NMOS transistor MN4, The parasitic capacitance introduced by the fifth NMOS transistor MN5, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 will greatly increase the capacitive load on the input end. To make the switch work normally, the driving capability of the input stage must be increased.

Furthermore, the gate-source voltage of the first NMOS transistor MN1 obtained from the above analysis is a fixed X. When it is necessary to obtain a lower on-resistance and increase the gate-source voltage, which is appropriately greater than X, this architecture is not applicable.

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