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A method for pcie data service quality management

A quality management and data service technology, which is applied in the field of PCIE data service quality management, can solve the problems of simple arbitration mechanism not optimized, consuming chip priority area, difficult to increase chip speed, etc., to achieve low power consumption, reduce chip area, The effect of reducing the occupied area

Active Publication Date: 2017-10-03
丁贤根
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  • Application Information

AI Technical Summary

Problems solved by technology

However, it consumes too much resources, and too many buffers of the receiving and sending ports consume the priority area of ​​the chip. The main performance is that each virtual channel uses its own cache, resulting in large chip area, high power consumption, and difficult improvement of chip speed; the QoS mechanism mainly uses Strict priority algorithm to achieve arbitration, the arbitration mechanism is simple and not optimized, the efficiency is not high, and it is easy to cause low-priority transactions to be blocked all the time

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  • A method for pcie data service quality management
  • A method for pcie data service quality management
  • A method for pcie data service quality management

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Embodiment Construction

[0028] Such as figure 2 As shown, a method for PCIE data service quality management, the buffers of the receiving end and the sending end share a buffer, and the data and the header of the packet are stored separately. This greatly reduces the area occupied by the original 16 buffers at both ends.

[0029] The PCIE protocol specifies the respective processing methods of data and packet headers. Data must be in double-word units, and packet headers need to be combined in accordance with the prescribed format.

[0030] Such as image 3 As shown, under the new structure, while the data path of the sender completes the basic transactions specified by PCIE, it also completes the QoS requirements of the PCIE transaction layer. Mainly on the premise of sharing the buffer, let the data to be sent and the header of the packet be sent in the manner specified in the agreement, while meeting the requirements of QoS, the amount of credit is controlled, the arbitration algorithm can be selected...

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Abstract

The invention relates to a technology for PCIE data service quality management. While the data path at the sending end completes the basic affairs stipulated by PCIE, it also completes the requirements for the data service quality of the PCIE transaction layer, mainly under the premise of sharing the buffer. The sent data and packet headers are sent according to the method specified in the protocol, while meeting the requirements of data service quality, the amount of credit is controlled, and the arbitration algorithm can be selected to effectively control the data to prevent data loss or blockage.

Description

Technical field [0001] The invention relates to a technology for PCIE data service quality management. Background technique [0002] With the rapid development of semiconductor technology, the integration of chips has been significantly improved, and the performance of computer processors and network cards has been greatly improved, but the speed of the bus connecting the processor and peripheral components has not increased. Since Intel created the Peripheral Interconnect Component (PCI) bus in 1992, the PCI bus has become the bus standard and has been in use ever since. The maximum bandwidth of the PCI bus is 133MB / s, but this limited bandwidth needs to be shared by devices such as network cards and graphics cards. For the 10 Gigabit network cards that have emerged now, the PCI bus bandwidth is obviously a drop in the bucket, and the bus bandwidth has become a bottleneck affecting the development of computers. Therefore, PCIE came into being under this background. [0003] Int...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/40H04L12/24
Inventor 林谷胡永鑫李冰丁贤根
Owner 丁贤根