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Communication system between FPGA (field programmable gate array) and computer

A communication system and computer technology, applied in the field of PCIe communication systems, can solve problems such as reducing system availability, increasing data transmission delay, and being difficult for users to use, and achieves the effect of accelerating research and development, improving efficiency, and saving time and manpower investment.

Active Publication Date: 2014-02-05
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this device can be used for communication between FPGA and computer, it can only support one algorithm acceleration logic device, which reduces the availability of the system
And there is no support for the system on the software side, which is not easy for users to use
And there are other devices in the data path of the device, which increases the data transmission delay and reduces the data transmission performance

Method used

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  • Communication system between FPGA (field programmable gate array) and computer
  • Communication system between FPGA (field programmable gate array) and computer

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach

[0033] A communication system between FPGA and computer, including: DMA engine, PIO engine, register bank, message controller, interrupt controller and PCIe IP core (see figure 1 );in,

[0034] A. The DMA engine includes a downlink DMA control module, a downlink DMA data processing module, an uplink DMA control module, and an uplink DMA data processing module, wherein,

[0035]a) The downlink DMA control module is used to control the DMA from the computer to the FPGA direction (DMA in this direction is also called DMA read), and perform DMA on the DMA descriptor according to the DMA read start and DMA read descriptor address signals given by the register group operation, and then control the downlink DMA data processing module to perform DMA read operation through the DMA address and DMA length information in the DMA descriptor;

[0036] b) The downlink DMA data processing module is used to process the DMA (DMA in this direction is also called DMA read) data from the computer...

Embodiment 1

[0053] Embodiment 1: DMA data transmission from computer to FPGA direction

[0054] Assuming that the communication system between the FPGA and the computer described in the present invention has received a DMA request from the user software, the character string "1234" starting at memory location 0x45000004 needs to be transmitted to the user FPGA application through DMA data transmission. And the software has placed the DMA descriptor describing the above DMA operation in memory 0x43000000.

[0055] The PIO engine of the communication system between FPGA of the present invention and the computer will receive two PIO write requests, first write in the DMA read operation descriptor address register in the register group, the value of writing is 0x43000000; The first write to the DMA read start register in the register bank. At this time, the downlink DMA control module detects the start of DMA reading, so it makes a data request according to the value 0x43000000 in the DMA re...

Embodiment 2

[0059] Embodiment 2: DMA data transmission from FPGA to computer direction

[0060] Assuming that the communication system between the FPGA and the computer described in the present invention has received a DMA request from the user software, the character string "5678" in the FPGA needs to be transferred to the computer, specifically the 4 characters starting from DMA to memory 0x46000004 section. The software has placed the DMA descriptor describing the above DMA operation at 0x44000000 in memory.

[0061] The PIO engine of the communication system between FPGA of the present invention and the computer will receive twice PIO write request, first time writes DMA in the register group and writes the descriptor address register, and the value of writing is 0x44000000; Write to the DMA write start register in the register bank. At this time, the upstream DMA control module detects the start of DMA writing, so it makes a data request according to the value 0x44000000 in the DMA...

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Abstract

The invention provides a communication system between an FPGA (field programmable gate array) and a computer. The communication system comprises a DMA (directly memory access) engine, a PIO (programmed input / output) engine, a register block, a message controller, an interrupt controller and a PCIe IP (peripheral component interface-express intellectual property) core. Full-duplex and high-throughput DMA data transmission is realized by a sending module and a receiving module which are stand-alone in FPGA hardware, low-delay data transmission is realized by stand-alone processing of data flow and control flow in the sending module or the receiving module, and the FPGA and the computer are linked together by the DMA data transmission. By utilizing the technical scheme provided by the invention, the efficiency of the integration of an FPGA application and the computer can be increased, the research and development speed, the testing speed and the speed to market of the FPGA application are picked up, and the time and the human input consumed by the integration of the FPGA application and the computer are saved.

Description

technical field [0001] The invention provides a communication system between an FPGA (Field-Programmable Gate Array, Field-Programmable Gate Array) and a computer, and in particular relates to an efficient and easy-to-use PCIe communication system between the FPGA and a computer. Background technique [0002] Field Programmable Gate Array (FPGA) is a programmable circuit device. With the development of FPGA technology, the resources in the FPGA chip continue to increase, and the functions and computing capabilities have also been greatly improved. Many researchers use FPGA to accelerate the algorithm. Therefore, efficient and easy-to-use communication between FPGA accelerators and computers has become a requirement. [0003] PCIe (PCI-Express, Express Peripheral Interconnection Standard) bus is a high-speed computer bus that uses a serial, point-to-point method to connect external devices of the computer. A single direction of a single link of the PCIe bus can reach a dat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28G06F13/38
Inventor 王韬龚健
Owner PEKING UNIV
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