Method for improving writing-in redundancy rate of static random access memory

A static random, write redundancy technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as low equivalent resistance and low write redundancy

Active Publication Date: 2014-02-12
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in the existing SRAM, the equivalent resistance of the pull-up transi...

Method used

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  • Method for improving writing-in redundancy rate of static random access memory
  • Method for improving writing-in redundancy rate of static random access memory
  • Method for improving writing-in redundancy rate of static random access memory

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Embodiment Construction

[0024] In order to illustrate the technical content, structural features, achieved goals and effects of the present invention in detail, the following will be described in detail in conjunction with the embodiments and accompanying drawings.

[0025] see figure 1 , figure 1 Shown is a schematic diagram of an equivalent circuit for writing in the SRAM of the present invention. Write margin (Write Margin) is an important parameter to measure the write performance of the SRAM unit. In the writing equivalent circuit of the SRAM, it is assumed that the first node 1 stores data at a low potential (that is, the stored data is "0"), and the second node 2 stores data at a high potential (that is, stores The data is "1"), non-limiting list, for example, writing a high potential to the first node 1, writing a low potential to the second node 2, before the writing action, the first bit line 3 will be precharged to a high potential, and the second bit line 4 will be precharged to a low ...

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Abstract

A method for improving the writing-in redundancy rate of a static random access memory comprises the first step of providing a silicon-based substrate and forming a shallow-channel isolator, the second step of forming an NMOS device and a PMOS device serving as an upwards-pull transistor, the third step of carrying out source-drain injection in source electrode areas and drain electrode areas of the NMOS device and the PMOS device serving as the upwards-pull transistor and depositing a silicon nitride protective layer, the fourth step of carrying out source-drain annealing process on the NMOS device and the PMOS device serving as the upwards-pull transistor, and the fifth step of etching and removing the silicon nitride protective layer. When a stress memory effect process photolithography mask is manufactured, the PMOS device area of the upwards-pull transistor and the NMOS device are covered; in the stress memory effect process, the upwards-pull transistor and the NMOS device are both covered with the silicon nitride protective layer, then the source-drain annealing process is carried out, the hole mobility of the upwards-pull transistor is reduced, and then the equivalent resistance of the upwards-pull transistor is increased; in the writing-in process, the electric potential of a second node is lowered and then the writing-in redundancy rate can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for improving write redundancy of a static random access memory. Background technique [0002] Static Random Access Memory (SRAM), as an important product in semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. [0003] Generally, the layout of the SRAM below 90nm includes three levels of active area, polysilicon gate, and contact holes, and control transistors are respectively formed on the layout area, and the control transistors are NMOS devices; pull-down transistors (Pull Down MOS), the pull-down transistor is an NMOS device; the pull-up transistor (Pull Up MOS), the pull-up transistor is a PMOS device. However, in the existing SRAM, the equivalent resistance of the pull-up transistor is small, which leads to a small write margin (Write Margin) of the SRAM. Seeking a method for inc...

Claims

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Application Information

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IPC IPC(8): H01L21/8244
CPCH01L29/66568H01L29/7843H01L29/7847H10B10/12
Inventor 俞柳江
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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