Plane gate type MOS tube and manufacturing method thereof
A MOS tube and planar gate technology, which is applied in the manufacture of planar gate MOS tubes and in the field of planar gate MOS tubes, can solve problems such as limited high-voltage resistance, affect the overall performance of the device, and large resistance, and achieve small forward conduction voltage Effect
Inactive Publication Date: 2014-02-12
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
Due to the limited high-voltage withstand capability of Schottky diodes, high-voltage diodes generally use PN junction diodes, which are characterized in that the larger the reverse bias voltage is, the wider the required breakdown-resistant depletion layer width is, and the wider the depletion layer width is. Wider will lead to greater resistance when the device is turned on in the forward direction, which will affect the overall performance of the device
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[0026] like figure 2 As shown, the planar gate MOS transistor of the present invention includes: a P well 3 in the formation of an N-type epitaxial layer or an N-type silicon substrate 1, and an N-type epitaxial layer on one side of the P well 3 or in the N-type silicon substrate 1 An N+ injection layer 4 is formed, and three serial MOS structures with identical manufacturing parameters and device structures are arranged side by side on the upper part of the P well 3;
[0027] The MOS structure includes: a gate oxide layer 2 formed on the P well 3, a polysilicon gate 5 formed on the gate oxide layer 2, and an N+ injection layer 4 formed in the P well 1 below the gate oxide layer 2;
[0028] Each polysilicon gate 5 is connected to the N+ injection layer 4 of its side MOS structure, and the N+ injection layer 4 in the N-type epitaxial layer or the N-type silicon substrate 1 is drawn out as a connection terminal a of the device, and the P well 3 is connected The N+ injection la...
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The invention discloses a plane gate type MOS tube and a manufacturing method of the plane gate type MOS tube. The plane gate type MOS tube comprises a P trap formed in an N-type epitaxial layer or an N-type silicon substrate. An N+ injection layer is formed in the portion, at one side the P trap, of the N-type epitaxial layer or the N-type silicon substrate and a plurality of MOS structures which are mutually connected in series are arranged on the upper portion of the P trap side by side. Each MOS structure comprises a gate oxide layer formed on the P trap, a polysilicon gate formed on the gate oxide layer and an N+ injection layer formed in the position, beside the lower portion of the gate oxide layer, of the P trap; each polysilicon gate is connected with an N+ injection layer of the MOS structure arranged adjacent to the polysilicon gate, the N+ injection layer in the N-type epitaxial layer or the N-type silicon substrate is led out to serve as one connection end of a device, the N+ injection layer, most far away from the N+ injection layer in the N-type epitaxial layer or the N-type silicon substrate, in the P trap is led out and serves as the other connection end of the device. Compared with a traditional high-voltage diode device, the plane gate type MOS tube has the advantages that the function of high-voltage-puncture resistance is achieved, small positive communicating voltage is obtained, and larger current power supply is achieved.
Description
technical field [0001] The invention relates to the field of integrated circuits, in particular to a planar gate type MOS transistor. The invention also relates to a method for manufacturing a planar gate type MOS tube. Background technique [0002] Currently, high-voltage diode devices are constructed of PN junctions or Schottky metal-semiconductor contacts. Due to the limited high-voltage withstand capability of Schottky diodes, high-voltage diodes generally use PN junction diodes, which are characterized in that the larger the reverse bias voltage is, the wider the required breakdown-resistant depletion layer width is, and the wider the depletion layer width is. Wider will lead to greater resistance when the device is turned on in the forward direction, which will affect the overall performance of the device. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a planar gate type MOS transistor which, compared wi...
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IPC IPC(8): H01L27/088H01L21/8234
Inventor 王飞钟秋
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP