Formation of a layout structure for ultra-high withstand voltage resistors

Abstract

The invention discloses a layout structure for forming an ultra-high withstand voltage resistance, which includes a high withstand voltage field effect transistor and a polysilicon resistor; the high withstand voltage field effect transistor includes a drain region, a source region, a drain region drift region and a drift region; the drain region Located in the center of the field effect transistor, the drain drift region is located between the drain region and the source region, and the source region is located outside the gate and surrounded by the drift region; field oxygen is formed in the drain region drift region, and the field oxygen is on the side near the drain region The polysilicon field plate in the drain region is formed, and the gate polysilicon is formed on the other side, and the gate polysilicon and the polysilicon field plate in the source region are connected laterally and connected to the source region; the polysilicon resistance is formed on the field oxygen and is located between the polysilicon field plate in the drain region and the gate polysilicon Between them, the high-voltage end is connected to the drain region of the high withstand voltage field effect transistor and the polysilicon field plate in the drain region through a metal wire, and the other end is led out through a metal wire. The invention utilizes the withstand voltage characteristics of the high withstand voltage field effect transistor to make the polysilicon resistance have the same withstand voltage capability as the high withstand voltage field effect transistor.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a layout structure of ultra-high withstand voltage (greater than 300V) resistors. Background technique [0002] Currently used polysilicon resistors such as figure 1 As shown, the field oxide 306 is usually grown on the silicon substrate 301, and then polysilicon is grown on the field oxide 306, through holes 302, 303 are drilled at both ends of the polysilicon, and metals 304, 305 are drawn out respectively to form a resistance structure. As long as the resistance of this structure is large enough (for example, greater than 10MΩ), the current is small enough under high voltage (about 100V), and the polysilicon itself will not be damaged (generally, the polysilicon will be damaged if the current is greater than 20mA / μm). However, when a high voltage is applied to the metal 305 at one end of the polysilicon and the metal 304 at the other end is grounded, since the...

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Problems solved by technology

However, when a high voltage is applied to the metal 305 at one end of the polysilicon and the metal 304 at the other end is grounded, since the silicon substrate 301 is connected to zero potential during chip operation, there is a high voltage difference between the polysilicon and the silicon substrate 301. The thickness of the field oxygen isolation between the polysilicon and the silicon substrate 301 is 4000A-6000A, so the polysilicon resistance can only withstand within 100V, and cannot provide higher withstand voltage applications

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