Method for designing mapping scheme and topological structure between task and node in on-chip network

Abstract

The invention discloses a method for designing a mapping scheme and a topological structure between a task and a node in an on-chip network. The method is characterized by comprising the steps that power consumption and response time are separated and used as preferential indexes for an appraisal program, the power consumption and the response time are simultaneously considered in the process of finding the optimal scheme, the aim of enabling the power consumption and the response time to be simultaneously minimum through the found scheme is achieved, and in addition, the topological structure enabling the power consumption and the response time to be minimum is selected.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a design method for mapping schemes and topological structures between tasks and nodes in a wireless on-chip network for multi-tasks and multi-nodes in an on-chip network. Background technique [0002] With the increasing computational complexity of communication terminals and equipment in the future, the demand for integration scale of real-time complex system chips will increase rapidly. Dozens or hundreds of processing units may be integrated on one chip, and signal processing based on multi-core Platform becomes the development trend of software defined radio. In such an integrated system, designing a reliable, high-speed, low-power-consumption high-performance on-chip communication system has become a challenge and an opportunity for the development of a System on Chip (SoC). The bus communication structure of the traditional multi-core SoC cannot meet the data exch...

AI Technical Summary

Problems solved by technology

This method can only be randomly arranged when dealing with the schemes with the same aggregation distance, which cannot reflect the actual situation well.

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