Semiconductor device and method for preparing same

Abstract

The present invention relates to a semiconductor device and a method for preparing the same. The method comprises the steps of providing a semiconductor substrate comprising a supporting substrate, an oxide insulating layer and a semiconductor material layer which are laminated orderly; forming a first hard mask layer on the substrate; patterning the first hard mask layer, the semiconductor material layer, the oxide insulating layer and a part of the supporting substrate to form a stepped substrate possessing a high area and a low area; forming a clearance wall on the side wall of the high area; growing the semiconductor material layer epitaxially in the low area, and peeling and flattening the rest of the first hard mask layer to form a mixed substrate; forming a second hard mask layer on the mixed substrate; etching the high area and the low area, etching the high area to the oxide insulating layer to form a first fin, and etching the low area below the oxide insulating layer to form a second fin. The method of the present invention is simpler and accurate, and enables the preparation efficiency and yield of the device to be improved further.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular, the invention relates to a semiconductor device and a preparation method thereof. Background technique [0002] The improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, manufacturing and design challenges have led to the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Typical FinFETs are fabricated using thin vertical "fins" (or fin structures) extending from a substrate formed, eg, by etching away a portion of the silicon layer. A FinFET channel is formed in the vertical fin, a surrounding gate is formed above the fin, and the channel is controlled from both sides through the gate. Additionall...

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Problems solved by technology

[0004] At present, it is difficult to control the height of the fins in the manufacturing process of the fin field effect transistor, and the existing preparation methods cannot solve this problem well, which affects the performance of the fin field effect transistor

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