How the transistor is formed

Abstract

Provided is a transistor forming method which comprises: providing a semiconductor substrate equipped with a dielectric layer on the surface thereof, wherein a first opening passing through the dielectric layer is arranged in the dielectric layer and is composed of a gate structure the surface of which is aligned to the surface of the dielectric layer, the gate structure comprises a gate dielectric layer on the bottom of the first opening, a work function layer covering the gate dielectric layer and the sidewall of the first opening, and a gate electrode layer arranged on the surface of the work function layer and fully filling the first opening, and the work function layer and the gate electrode layer are produced by metal material; etching the work function layer in order that the top surface of the work function layer is lower than that of the dielectric layer; etching the gate electrode layer after etching the work function layer in order that the surface of the gate electrode layer is lower than that of the dielectric layer but higher than that of the work function layer; forming an insulating layer on the surfaces of the gate electrode layer and the work function layer after etching the gate electrode layer in order that the surface of the insulating layer is aligned to the surface of the dielectric layer and the material of the insulating layer is different from the material of the dielectric layer. A formed transistor has excellent performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits, especially MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) devices, is continuously reduced to meet the miniaturization and integration of integrated circuit development. requirements. In the process of continuous shrinking of the size of MOS transistor devices, the process of using silicon oxide or silicon oxynitride as the gate dielectric layer in the existing process is challenged. Transistors formed with silicon oxide or silicon oxynitride as the gate dielectric layer have some problems, including increased leakage current and diffusion of impurities, which affect the threshold voltage of the transistor and further affect the performance of semicondu...

AI Technical Summary

Problems solved by technology

[0005] However, the transistor performance of the prior art high-K dielectric layer and metal gate structure is not good

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