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Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., to achieve the effects of reducing capacitive coupling, increasing the scale of circuit integration, and reducing parasitic coupling effects

Inactive Publication Date: 2014-05-14
李迪
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the distance is small to a certain extent, the problem of capacitive coupling between adjacent memory cells becomes prominent, which seriously limits the further improvement of storage density, so it is urgent to find a way to solve this problem

Method used

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  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof

Examples

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Embodiment Construction

[0025] Embodiments of the present invention are described in detail below.

[0026] Examples of the described embodiments are shown in the drawings, wherein like or similar reference numerals designate like or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and / or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in i...

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Abstract

The invention provides a manufacturing method of a semiconductor structure. The method comprises the following steps: a) a substrate is provided, and the substrate comprises a first direction and a second direction; b) a gate stack is formed on the substrate, and the grid stack comprises a first insulating layer and a floating gate in turn; c) the floating gate is etched in the first direction so that at least two recesses are formed on the side wall of the floating gate in the first direction; d) a second insulating layer and a control gate are formed on the floating gate via deposition, and the second insulating layer and the control gate cover the side surface of the floating gate in the first direction; e) the floating gate is etched in the second direction so that at least two recesses are formed on the side wall of the floating gate in the second direction; and f) source / drain regions are formed on the two sides of the stack gate. Correspondingly, the invention also provides the semiconductor structure. Capacitive coupling between two adjacent lists of units can be reduced and the capacitive coupling between the control gate and the floating gate can be enhanced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) is user-alterable Read-Only Memory (ROM) that can be erased and reprogrammed (rewritten) by the application of higher than normal voltages. Unlike EPROM chips, EEPROMs can be modified without being removed from the computer. In an EEPROM, it is reprogrammable frequently when the computer is in use, so the application of EEPROM is more and more extensive. [0003] EEPROM adopts a double-layer gate (two-layer polysilicon) structure, that is, a layer of polysilicon gate is added under the silicon gate of the conventional MOS transistor. This layer of silicon gate is not connected to the outside world and is completely covered by insulating layer materials (such as silicon dioxide, nitrogen, etc. silicon etc.) and the surrou...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L21/28H01L27/115H01L29/423H01L29/788H10B69/00
CPCH01L29/40114H01L29/42324H01L29/788H10B41/00
Inventor 李迪
Owner 李迪
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