Structure of planer phase change memory storage unit and manufacturing method thereof

Abstract

The invention provides a structure of a planer phase change memory storage unit and a manufacturing method of the planer phase change memory storage unit. The structure of the planer phase change memory storage unit and the manufacturing method of the planer phase change memory storage unit solve the problem of compatibility of a phase change storage unit in an existing phase change memory and a CMOS logic process, use a physical gas-phase deposition technology, and omit the step of manufacturing a heating electrode. In the manufacturing process of the planer phase change memory storage unit, a metal organic chemical gas-phase deposition technology or atom layer deposition technology with quite high cost does not need to be adopted to grow phase-change materials, and good performance can be achieved only through the ordinary physical gas-phase deposition technology. Besides, compared with the CMOS logic process, only one mask is added in the entire manufacturing process, production cost and manufacturing difficulty are largely lowered, and influence on circuit performance is avoided for CMOS transistors.

Description

technical field [0001] The invention relates to a semiconductor device structure and its preparation technology, in particular to a structure of a planar phase-change memory storage unit and a preparation method thereof. Background technique [0002] Phase-change memory is an emerging non-volatile memory technology. It uses electrical pulses to rapidly transform phase-change materials in an ordered crystalline state (low resistance) and a disordered amorphous state (high resistance). Realize data storage. Phase-change memory is non-volatile, fast, easier to shrink to a smaller size, and has high reliability. It is likely to be a replacement for flash memory technology. [0003] In order to make the phase change memory compatible with the logic process, the general structure adopted is as follows figure 1 shown. Among them, 1-phase-change material layer, 2-upper electrode of phase-change memory cell or upper connection hole of transistor, 3-lower connection hole, 4-insulat...

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Problems solved by technology

The unit area of ​​this three-dimensional phase-change memory unit can be made very small, but it has high requirements on the process. Generally, atomic layer deposition (ALD) technology is required. This kind of equipment is expensive, and some old manufacturing plants do not have this equipment.

Moreover, compared with the CMOS logic process, this three-dimensional structure adds 3-10 masks (mask), which greatly increases the production cost.

When growing phase change materials by physical vapor deposition or atomic layer deposition (generally the main materials are synthetic materials of germanium, antimony and tellurium (Ge 2 Sb 2 Te 5 ), mostly known as GST), mainly encounter the following bottlenecks: (1) phase change materials will shrink in volume during the preparation of CMOS logic technology, which will affect the connectivity rate of the subsequent metal interconnection layer; (2) if figure 1 The CMOS transistor with this structure shown has the upper connection hole 2 and the lower connection hole 3 compared with the phase change memory technology, which has an impact on the performance of the transistor, especially in high-speed logic circuits, based on pure CMOS technology. Libraries need to be regenerated

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