Control circuit of charge pump and charge pump circuit

Abstract

The invention discloses a control circuit of a charge pump and a charge pump circuit. The control circuit of the charge pump comprises a sampling circuit, a voltage comparator, a single-side signal delayer and a clock control signal acquisition circuit, wherein the sampling circuit is suitable for sampling the output voltage of the charge pump to obtain sampling voltage; the first input end of the voltage comparator is suitable for inputting the sampling voltage, the second input end of the voltage comparator is suitable for inputting reference voltage, and the output end of the voltage comparator is suitable for outputting a first enabling signal; the single-side signal delayer is suitable for delaying the falling edge of the first enabling signal to obtain a second enabling signal; the clock control signal acquisition circuit is suitable for outputting a clock control signal to the charge pump when the second enabling signal is at a high level.

Description

technical field [0001] The invention relates to a charge pump control circuit and a charge pump circuit. Background technique [0002] A charge pump circuit is a circuit that uses the accumulation of charges in a capacitor to generate a high voltage, and it is widely used in memory circuits. [0003] figure 1 It is a structural schematic diagram of an existing charge pump circuit, and the charge pump circuit includes: a charge pump 1, a first resistor R1, a second resistor R2, a voltage comparator 2, a NAND gate circuit 3, an inverter 4, a clock generator 5 and load capacitor C1. [0004] The output terminal OUT of the charge pump 1 is connected to the first terminal of the first resistor R1 and the first terminal of the load capacitor. The charge pump 1 may be a four-phase charge pump. [0005] The second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and the first input terminal of the voltage comparator. The second end ...

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Problems solved by technology

[0012] In the voltage adjustment stage, the sampling voltage VDET is continuously compared with the reference voltage VREF to generate the enable signal EN, and the charge pump 1 will switch frequently under the action of the enable signal EN to maintain the output voltage of the charge pump at the target value. However, the constant frequency band switching of the charge pump will generate a lot of power consumption

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