Self-alignment process for tsv back leak hole and dielectric layer and tsv

Abstract

The invention provides a self-alignment technology for leak holes and a dielectric layer on the back of a TSV and the TSV. The self-alignment technology comprises the following steps that a substrate with TSV blind hole structure manufacturing finished is provided; back thinning is carried out on the substrate, and the etching technology is used for enabling the back end of the TSV to protrude out of the surface of the back of the substrate; the back face of the substrate is coated by the back dielectric layer which covers the back face of the substrate and the TSV back end protruding out of the back surface of the substrate; the CMP technology is used for carrying out flattening processing on the back dielectric layer, and the TSV is made to be exposed; the etching technology is used for processing the exposed TSV, and steps of the TSV and the back dielectric layer are formed; an adhesion layer and a seed layer are deposited on the back face of the substrate; the steps of the TSV and the back dielectric layer are used for carrying out photoetching alignment on micro salient points or RDL, and the technology of manufacturing the micro salient points or the RDL is completed. The self-alignment technology can prevent metal from polluting the silicon substrate, and photoetching precision when the micro salient points or the RDL is manufactured is guaranteed.

Description

Technical field [0001] The present invention relates to a microelectronic packaging process, in particular to a self-alignment process for TSV backside leakage holes and dielectric layer and TSV. Background technique [0002] In microelectronics packaging, a simple and reliable TSV backside connection process is required. The existing connection technology on the back of TSV usually uses the following methods: [0003] 1. Grind and thin the back surface of the substrate with the TSV blind via structure. [0004] 2. Perform a CMP (chemical mechanical polishing) process on the back of the substrate until the TSV leak hole, but at this time the Si of the substrate and the Cu (copper) of the TSV are exposed at the same time, which may cause the metal to contaminate the silicon substrate. [0005] 3. Make a dielectric layer on the back of the substrate. [0006] 4. Use the double-sided alignment process to pattern the backside dielectric layer, that is, first use the alignment marks on the...

AI Technical Summary

Problems solved by technology

[0004] 2. Perform CMP (Chemical Mechanical Polishing) process on the back of the substrate until the TSV leaks, but at this time the Si of the substrate and the Cu (copper) of the TSV are exposed at the same time, which may cause contamination of the metal to the silicon substrate

[0007] The double-sided alignment process used in this method has poor alignment accuracy and requires a relatively good flatness on the back of the wafer. It is only suitable for the process of using CMP to make TSV leaks, which may cause contamination of the metal on the silicon substrate.

Images