A flip-flop design method against single-event upset and single-event transient pulse

Abstract

The invention discloses a method for designing a trigger resistant to single event upset and single event transient pulses. The method for designing the trigger resistant to the single event upset and the single event transient pulses comprises the steps of circuit reinforcing design and diagram reinforcing design. According to the circuit reinforcing design, a redundant clock DICE trigger circuit with delay filtering is designed based on the DICE structure according to the 0.13-micron bulk silicon CMOS technology. According to the diagram reinforcing design, the distance between storage nodes in the DICE trigger circuit is increased, and the area of a drain region is reduced. The method for designing the trigger resistant to the single event upset and the single event transient pulses has the advantages that the phenomenon of clock overlapping is avoided, power dissipation is reduced, the SEU / SET resistance of the trigger is further improved, cost is low, and the reliability is high.

Description

Technical field [0001] The invention relates to a trigger design method for resisting single event flipping and single event transient pulse, and belongs to CMOS integrated circuit space single event effect protection technology. Background technique [0002] In the space radiation environment, CMOS integrated circuits are susceptible to single event flipping and single event transients, which can cause abnormal device functions. figure 1 It is a cross-sectional view of a CMOS inverter. If its input terminal is connected to a low level, the output is high. When high-energy ions pass through the device, electron-hole pairs are generated in their path. Under the action of the electric field, holes drift to the source end of the NMOS transistor, and electrons drift to the drain end of the NMOS transistor. When these electrons accumulate to a certain extent, the potential of the drain terminal will be pulled from high to low, causing the logic of the output terminal to change from 1...

AI Technical Summary

Problems solved by technology

SET generally occurs in combinational circuits, but errors caused by SET may be sampled by flip-flops or memories, causing SEU

[0005] At present, most of the anti-SEU circuit-level hardening technologies for flip-flop units are based on the traditional dual interlocking cell (DICE) structure. In the traditional DICE structure, the clock signal is easily disturbed by SET, which will cause the flip-flop to accidentally capture data at the wrong time. ; At the same time, the structure has a weak SET protection ability for the data input end, which will cause the trigger to collect wrong data

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