Sige body region vertical 1t-dram device and its manufacturing method

Abstract

The present invention provides a vertical nanocolumn 1T-DRAM device and array based on SiGe energy band engineering, which adopts a vertical nanocolumn transistor, and uses epitaxy to form a stacked layer respectively as a channel region and a drain region. The design of the drain region provides a large space, which provides many implementation solutions for the improvement of 1T-DRAM performance; at the same time, the structure of the vertical transistor is conducive to the integration of the SiGe channel region, using epitaxial SiGe as the channel region, using SiGe and The difference in Si valence band creates a potential well of holes in the channel region, which can effectively increase the current difference between the read 1 state and the read 0 state of 1T-DRAM.

Description

technical field [0001] The invention relates to the field of semiconductor devices and manufacturing methods thereof, in particular to a vertical high-integration transistor structure based on SiGe energy band engineering and a manufacturing method thereof. Background technique [0002] With the continuous shrinking of the feature size of semiconductor integrated circuit devices, the size of the traditional 1T / 1C embedded DRAM unit is shrinking, and the area of ​​its capacitor is becoming more and more difficult as scaling down, and the manufacturing process is also becoming more and more difficult. Complicated, and the compatibility with the logic device process is getting worse. Therefore, capacitorless DRAM (Capacitorless DRAM) with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM of VLSI. Among them, 1T-DRAM (One Transistor Dynamic Random Access Memory) utilizing floating body effect is the main i...

AI Technical Summary

Problems solved by technology

[0005] At present, the structure of IT-DRAM is generally based on SOI planar structure, and the main problem of 1T-DRAM with SOI planar structure is that the potential of the body region is limited by the hole barrier between the body region and the source and drain.

In addition, the SOI substrate is not compatible with the currently widely used bulk silicon process, and there is a problem that it is not easy to dissipate heat

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