Integrated passive capacitor fan-out wafer-level packaging structure and manufacturing method

Abstract

The invention relates to an integrated passive capacitance fan-out wafer-level packaging structure and a manufacturing method, including a plastic package and a chip; the feature is that a first metal post, a second metal post, a third The first metal post and the second metal post are located on one side of the chip, and the third metal post and the fourth metal post are located on the other side of the chip; The first metal layer, the second metal layer, the third metal layer and the fourth metal layer are arranged in the layer, the first metal layer is connected with the first metal column, the second metal layer is connected with the second metal column and the first electrode, and the second metal layer is connected with the first metal column and the first electrode. The third metal layer is connected to the third metal column and the second electrode, and the fourth metal layer is connected to the fourth metal column; the metal layer under the bump is respectively arranged on the four metal layers, and the solder is respectively arranged on the outer surface of the metal layer under the point. ball. The invention realizes the integration of fan-out chip packaging and thin-film integrated passive passive devices, and improves the electrical quality.

Description

technical field [0001] The invention relates to an integrated passive capacitor fan-out wafer-level packaging structure and a manufacturing method, and belongs to the technical field of fan-out wafer-level packaging. Background technique [0002] Wafer-level fan-out chip packaging can replace the current bonded BGA (Ball Grid Array, PCB with ball grid array structure) and flip-chip BGA packaging. It is a low-cost, high-performance integrated packaging method. The signal, power and ground wiring of wafer-level fan-out chip packaging is directly realized through the wafer-level RDL (redistribution layer) process, which eliminates the need for wafer bump preparation and packaging substrates, thereby reducing packaging costs and can Provides better electrical performance than conventional wire bond BGA and flip chip BGA packages. Thin-film integrated passive technologies generally offer the best functional density, as well as the highest integration and lightest volume. Howeve...

AI Technical Summary

Problems solved by technology

Existing integrated passive capacitors are limited by the semiconductor material properties of silicon materials, and cannot improve the quality factor of their circuits

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