Semiconductor device and manufacturing method thereof

Abstract

Disclosed is a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate; a well region in the semiconductor substrate; The semiconductor fins, and the respective back gate dielectrics that separate the back gate conductors from the semiconductor fins, wherein the well region serves as a part of the conductive path of the back gate conductors; the punch-through prevention layer located at the lower part of the semiconductor fins; A front gate stack where the sheets intersect, the front gate stack includes a front gate dielectric and a front gate conductor, and the front gate dielectric separates the front gate conductor from the semiconductor fin; and a source region connected to a channel region provided by the semiconductor fin and Drain area. The semiconductor device can realize high integration and low power consumption.

Description

technical field [0001] The present invention relates to semiconductor technology, and more particularly, to a semiconductor device including a fin (Fin) and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, it is desired to reduce power consumption while reducing the size of semiconductor devices to increase integration. To suppress the short-channel effect due to size reduction, FinFETs formed on SOI wafers or bulk semiconductor substrates have been proposed. A FinFET includes a channel region formed in the middle of a fin of semiconductor material, and source / drain regions formed at both ends of the fin. The gate electrode surrounds the channel region at least on both sides of the channel region (ie a double gate structure), thereby forming an inversion layer on each side of the channel. Since the entire channel region can be controlled by the gate, it can play a role in suppressing the short channel effect. ...

AI Technical Summary

Problems solved by technology

[0003] Despite their respective advantages, a semiconductor device that combines the advantages of both has not been proposed because of the many difficulties in forming the back gate in FinFETs.

In FinFETs based on bulk semiconductor substrates, due to the small contact area between the semiconductor fins and the semiconductor substrate, the formed back gate will cause serious self-heating effects

In FinFET based on SOI wafer, there is a problem of high cost due to the high price of SOI wafer

Moreover, the formation of the back gate on the SOI wafer requires precise control of ion implantation, through the top semiconductor layer to form the implantation region for the back gate under the buried insulating layer, resulting in difficulties in the process and low yield, and due to the impact on the trench Unintentional doping of the channel region leads to fluctuations in device performance

Images