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Forming method of metal interconnection structure

A metal interconnection structure and metal interconnection technology, applied in the field of semiconductor technology, can solve problems such as process influence and semiconductor device performance influence

Inactive Publication Date: 2014-09-17
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] After the above process, it will be found that there are some burr-like defects (defect) 5 at the bottom of the metal interconnection groove 81, and the existence of the burr-like defects 5 will affect the subsequent manufacturing process, thereby affecting the performance of the formed semiconductor device. , need a way to solve this problem

Method used

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  • Forming method of metal interconnection structure
  • Forming method of metal interconnection structure
  • Forming method of metal interconnection structure

Examples

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Embodiment 1

[0044] In this example, combined with Figure 7 to Figure 13 The method for forming a metal interconnection structure provided in the technical solution of the present invention applied in the double damascene process will be described in detail.

[0045] like Figure 7 As shown, a semiconductor structure is provided, and the semiconductor structure includes: a metal layer 400, an etch stop layer 401 covering the surface of the metal layer 400, a dielectric layer 300 located on the etch stop layer 401, and covering the The second mask layer 100 of the dielectric layer 300 .

[0046] In this embodiment, the second mask layer 100 is a photoresist, and a second mask pattern 700 is formed therein, and the second mask pattern 700 is an etching pattern of a through hole.

[0047] In this embodiment, the dielectric layer 300 is a multilayer structure, including a first interlayer dielectric layer 302 , a first mask layer 200 , and a second interlayer dielectric layer 301 from botto...

Embodiment 2

[0068] In this example, combined with Figure 14 to Figure 15 The method for forming a metal interconnection structure provided in the technical solution of the present invention applied in a single damascene process will be described in detail.

[0069] like Figure 14 As shown, a semiconductor structure is provided, and the semiconductor structure includes a metal layer 400 , a single-layer interlayer dielectric layer 300 , and a first mask layer 100 formed on the interlayer dielectric layer 300 .

[0070] In this embodiment, a TEOS layer 101 is further formed between the interlayer dielectric layer 300 and the first mask layer 100 , and an etching stop layer 401 is further formed between the metal layer 400 and the interlayer dielectric layer 300 .

[0071] In this embodiment, the first mask layer 100 is TiN, and has a first mask pattern 800 therein, and the mask pattern 800 is an etching pattern of a through hole. In other implementation manners, the first mask pattern 8...

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Abstract

The invention relates to a forming method of a metal interconnection structure. The forming method comprises the following steps that: a semiconductor structure is provided, wherein a metal layer, a first interlayer dielectric layer, and a first mask layer are formed at the semiconductor structure from bottom to top, the first mask layer has a first mask pattern, and the metal layer contains Cu and the first mask layer contains Ti; first etching is carried out on the first interlayer dielectric layer along the first mask pattern of the first mask layer and is stopped before the metal layer is exposed; cleaning processing is carried out by using mixed gas containing fluorocarbon gas and Ar; second etching is carried out on the semiconductor structure that has been cleaned along the first mask pattern by using the first mask layer as the mask to expose the metal layer. According to the technical scheme, further cleaning processing is carried out before the metal layer is exposed, thereby solving a problem that burr occurs at the bottom of the metal interconnection structure in the prior art can be solved. Moreover, the method is simple and the effect is obvious.

Description

technical field [0001] The invention relates to semiconductor process technology, in particular to a method for forming a metal interconnection structure. Background technique [0002] At present, the damascene process is usually used in the integrated circuit manufacturing process to form copper metal lines and metal vias connecting the copper metal lines in the adjacent upper and lower layers; the damascene process has become a common process in the semiconductor process. For related technologies, please refer to the publication number PCT application of WO2010 / 007477. [0003] In the actual process, many metal interconnection grooves and many through holes cooperate to form a metal interconnection structure on the entire silicon wafer. The following combination Figure 1 to Figure 5 , to form a metal interconnect structure in which a through hole and a metal interconnect groove communicate with each other. A brief introduction to the existing damascene process: [0004]...

Claims

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Application Information

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IPC IPC(8): H01L21/768
CPCH01L21/76814H01L2221/101
Inventor 张城龙胡敏达
Owner SEMICON MFG INT (SHANGHAI) CORP