Semiconductor device and manufacturing method thereof

A device manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems that it is difficult to effectively control the effect of the barrier layer, the position and thickness of the barrier layer, etc., and achieve the suppression of parasitic trenches channel and channel punch-through effect, improve device reliability, and simplify the process

Active Publication Date: 2018-09-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this process requires additional implantation steps and it is difficult to effectively control the position and thickness of the barrier layer, as well as properties such as the doping concentration of the doped barrier layer, making it difficult to effectively control the effect of the barrier layer

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Embodiment Construction

[0023] The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with schematic embodiments, and a three-dimensional multi-gate FinFET capable of effectively suppressing parasitic channel effects and a manufacturing method thereof are disclosed. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or manufacturing processes . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

[0024] It is worth noting that the upper part of each of the following figures is the device along the Figure 12 The cross-sectional view of the first direction (fin extension direction, source-...

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Abstract

The invention discloses a semiconductor device manufacturing method which comprises the following steps: forming a plurality of fins extending along a first direction and trenches on a substrate; forming a shallow trench isolation in the trenches, wherein the shallow trench isolation at least includes one doped isolating layer; and carrying out annealing to enable impurities in the doped isolating layers to be diffused into an adjacent substrate channel to form a punch-through barrier layer. According to the semiconductor device and the manufacturing method thereof of the invention, a plurality of stacks of doped layers and isolating layers are formed in the trenches on the sides of the fins and the uniform and steep punch-through barrier layer is formed through annealing and diffusion, which effectively restrains the parasitic channel effect and the channel punch-through effect, simplifies the process, and improves the reliability of the device.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional multi-gate FinFET capable of effectively suppressing parasitic channel effects and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control ability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/762H01L29/78H01L29/10
CPCH01L29/66803
Inventor 殷华湘洪培真孟令款朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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