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Method for Constraining Safe Operating Area Trajectories of Power Semiconductor Devices

A technology of power semiconductor and safe working area, applied in semiconductor devices, electric solid state devices, instruments, etc., can solve the problem that the peak power is not significantly constrained

Active Publication Date: 2017-01-11
ROBERT BOSCH AUSTRALIA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the peak power is not significantly constrained when the drain current and drain-source voltage are at peak levels

Method used

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  • Method for Constraining Safe Operating Area Trajectories of Power Semiconductor Devices
  • Method for Constraining Safe Operating Area Trajectories of Power Semiconductor Devices
  • Method for Constraining Safe Operating Area Trajectories of Power Semiconductor Devices

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Embodiment Construction

[0033] now refer to figure 2 , the positive offset safe operating area (SOA) trajectory 12 for the maximum ratio of the power semiconductor device is shown in graph 22 . As noted above, the SOA locus 12 represents the maximum simultaneous source-drain voltage and drain current that the power MOSFET can safely handle. In an embodiment of the present invention, the SOA trace 12 is constrained into a constrained SOA trace 24 with an N-channel enhancement mode power MOSFET in a high-side configuration between the power supply and the load. Those skilled in the art will appreciate that graph 22 may depict SOA trajectories for other devices, such as BJTs. Nevertheless, it can be seen that the source-drain voltage of the power MOSFET is constrained and the peak power generation as well as the total energy absorption of the power MOSFET is constrained to minimize the use of the SOA of the power MOSFET.

[0034] Constrained SOA trajectory 24 is generated according to the method desc...

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Abstract

A method for constraining a safe operating area (SOA) locus of a power semiconductor device between a power supply and a load during operation of the power semiconductor device, the method comprising: taking voltage measurements across the load (VLOAD); select a scalar to scale the obtained voltage measurement across the load (VLOAD); and configure the control circuit for control based on the product of the scalar and the voltage measurement across the load (VLOAD) The power semiconductor device controls the voltage, thereby constraining the output voltage of the power semiconductor.

Description

technical field [0001] The present invention relates to methods and circuits for constraining the safe operating area (SOA) trajectory of a power semiconductor device located between a power supply and a load during operation of the power semiconductor device. The present invention has particular but not exclusive application to constraining the SOA locus of an N-channel enhancement mode power MOSFET in a high-side configuration between a power supply and a load by constructing a control voltage for controlling the power MOSFET to constrain the power MOSFET's The output voltage. Background technique [0002] Power semiconductor devices, such as power metal oxide semiconductor field effect transistors (MOSFETs), are typically used to switch power ON and OFF to inductive loads, eg, in automatic control and pulse width modulated motor control applications. The power MOSFET has a gate electrode for controlling the power MOSFET, a drain electrode connected to the power source, a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05F1/56
CPCH01L2924/0002H03K17/0822H01L2924/00
Inventor T·罗科
Owner ROBERT BOSCH AUSTRALIA
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