An n-channel field-effect transistor with anti-single event effect and its manufacturing method
An anti-single event effect and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as increasing circuit response time, reduce transient current pulse time and peak value, improve The effect of radiation resistance, charge amount and absorption time reduction
Active Publication Date: 2017-09-26
XIANGTAN UNIV
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[0004] The hardening methods for single event transients can be divided into two types: device level hardening and circuit level hardening. The most common type of circuit level hardening is the triple redundancy circuit hardening method, but this method needs to sacrifice a lot of circuit area. Will increase circuit response time
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[0015] The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.
[0016] Such as figure 1 as shown, figure 1 It is a schematic cross-sectional structure diagram of an N-channel field-effect transistor resistant to single event effect of the present invention. 101 is a heavily doped substrate; the epitaxial layer 102 is grown on the substrate 101; on the epitaxial layer 102, the drain region 110 and the source region 111 are located at both ends; the first threshold voltage injection region 103 is located at the drain region 110 and the source region 111, on which is the gate oxide layer and the gate; the drain region electrode 108 is connected to the drain region 110, and connected to the voltage V DD The deep doped drain region 105 is located on the epitaxial layer 102, on the right side of the drain region 110; between the deeply doped drain region 105 and the drain region 110 is the second threshold voltage inj...
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The invention discloses an anti-single event effect N-channel field effect transistor and a manufacturing method thereof. The single event resistant N-channel field effect transistor includes a semiconductor substrate, an epitaxial layer, a source region, a drain region, and a gate, and a first threshold voltage injection region is arranged between the source region and the drain region, and the drain region An annular deep-doped drain region is arranged on the periphery, and a second threshold voltage injection region is arranged between the deep-doped drain region and the drain region. The invention surrounds a circle of deeply doped drain region on the periphery of the drain region of the traditional N-channel field effect transistor, and the additional deeply doped drain region can effectively assist the drain region to collect charges after the funnel effect is generated in the single particle incident sensitive drain region, so that the device After being irradiated by a single particle, the amount of charge absorbed by the drain region and the absorption time are reduced, which reduces the single particle transient current pulse time and peak value, and shields the single particle with a certain linear energy transmission value in the inverter chain. The transient voltage pulse improves the anti-irradiation ability of the device.
Description
technical field [0001] The invention relates to integrated circuit technology, in particular to an anti-single event effect N-channel field-effect transistor with anti-radiation capability and a manufacturing method thereof. Background technique [0002] Radiation will have a serious impact on the performance of integrated circuits, and the radiation environment mainly causes two effects on integrated circuits: total dose effect and single event effect. With the advancement of microelectronics technology, the feature size of devices is getting smaller and smaller, the impact of total dose effect on integrated circuits has become weaker and weaker, while the impact of single event effect is increasing. [0003] The single event effect means that when a single high-energy particle penetrates the sensitive area of an electronic device, it causes ionization and deposits charges on its trajectory. These deposited charges are collected by the sensitive area, causing the logic st...
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IPC IPC(8): H01L27/105H01L29/78H01L21/8238H01L21/76
Inventor 唐明华徐新宇燕少安张万里
Owner XIANGTAN UNIV