Lead frame structure with staggered pins and semiconductor device manufacturing method

Abstract

The invention provides a base-pin-staggering-mode-based lead frame structure and a semiconductor device manufacturing method. The lead frame structure formed on a substrate comprises a plurality of chip units; each chip unit includes at least one chip bench; a plurality of outer base pins are led out outwardly from a plurality of inner lead pins around each chip bench; and outer base pin regions of the adjacent chip benches are overlapped. In addition, the semiconductor device manufacturing method comprises: a silicon wafer is bonded to the chip benches of the base-pin-staggering-mode-based lead frame structure; all welding plates of the silicon wafer are coupled with the inner lead pins in the lead frames; resin molding is carried out; aging is carried out in a high-temperature environment; overflow connecting ribs are cut off; parallel testing is carried out; and cutting is carried out to form a semiconductor device. According to the invention, the staggered pin mode is introduced into the frame design; and the space occupied by the outer base pins between the two parallel chip benches can be reduced, so that the outer base pin regions of the two parallel chip benches are overlapped. Moreover, the outer frame connecting ribs are arranged and parallel electric performance testing can be realized.

Description

technical field [0001] The invention relates to a lead frame structure, in particular to a lead frame structure with staggered pins that rationally uses the area of ​​the base material and improves the ratio of the effective chip area to the entire lead frame, and a semiconductor device manufacturing method using the structure. Background technique [0002] In the process of chip fabrication, traditional chip packaging forms a plurality of chip units 10 arranged in matrix on the substrate 100 . The following is an example of a chip package arranged in an array: figure 1 A schematic diagram showing a substrate of a prior art chip package. Such as figure 1 As shown, a traditional chip package adopts a 5x3x8 array, and a total of 120 chip units 10 are formed on a substrate 100, that is, a lead frame of 120 products is integrated on a substrate of 57mmx215.7mm. [0003] figure 2 A schematic diagram showing the structure of a chip unit in a substrate of a chip package in the...

AI Technical Summary

Problems solved by technology

This leads directly to waste of lead frame material

[0007] (2) For the process based on the whole frame as the smallest operation unit (such as mold sealing, etc.), since the number of effective products at one time is only 120, this greatly affects the work of the corresponding station efficiency

[0008] (3) Since the chip stage and the pins are connected together before final molding and separation, it is difficult to implement frame-based parallel online testing

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