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A Fast Repair Method of Clock Skew in FPGA Implementation

A clock skew and repair method technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as excessive clock skew, timing failure to converge, etc., to improve reliability, reduce skew, and reduce hardware resources. the effect of occupancy

Active Publication Date: 2017-03-22
NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The technical problem to be solved by the present invention is that in the FPGA design of high-speed VLSI, the clock skew between the frequency division clock and the main clock is too large, resulting in that the timing cannot be converged

Method used

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  • A Fast Repair Method of Clock Skew in FPGA Implementation
  • A Fast Repair Method of Clock Skew in FPGA Implementation

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Embodiment Construction

[0021] In order to make the object of the present invention, the technical scheme clearer, the following specific examples in conjunction with the attached figure 1 And attached figure 2 Embodiments of the present invention will be further described in detail.

[0022] S1: Use QuartusII to perform logic synthesis and layout of the FPGA design source RTL code to obtain the initial layout diagram;

[0023] S2: Perform timing analysis on the initial layout and wiring diagram to obtain an initial timing report, and check the content of the initial timing report to determine whether the timing is converged; if the timing is converged, complete clock skew repair; if the timing is not converged, perform step S3;

[0024] S3: insert a delay chain in the main clock path;

[0025] First insert a delay chain composed of multiple ordinary buffers (LCELL) on the main clock path to adjust the delay time of the main clock, and insert a global buffer (global buffer) after the delay chain; ...

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Abstract

The invention discloses a quick fix method for clock skews in FPGA (field programmable gate array) realization and relates to the field of FPGA design for high-speed very large scale integrated circuits. By the method, the skews between two clocks are decreased to the greatest extent, and the problem of time sequence violation is solved effectively. According to the method, relative time delay of a main clock and a frequency division clock is controlled accurately by means of manually inserting a clock delay chain, locking a clock module in a designated area, manually allocating global buffers to the clocks and the like, and accordingly the purpose of decreasing skews between the two clocks is achieved. The method can be applied to all high-speed very large scale integrated circuit designs realized based on an FPGA.

Description

technical field [0001] The invention relates to the FPGA design field of high-speed ultra-large-scale integrated circuits, in particular to a fast repair method for clock skew in FPGA implementation. Background technique [0002] With the rapid development of FPGA (Field Programmable Gate Array, Field Programmable Gate Array) technology, its capacity is continuously increased, its speed is continuously improved, and its cost and power consumption are continuously reduced. FPGA is widely used in various fields of electronic design. The core circuits of more and more complex systems are realized by FPGA, and the prototype verification of chip design is carried out based on FPGA. [0003] However, with the continuous expansion of the scale and speed of FPGA devices, more and more designs will encounter timing closure problems, whether using FPGAs for design implementation or prototype verification. How to ensure and improve timing closure is the key to current FPGA design. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 杨松芳张勇常迎辉曾明田素雷吕杰
Owner NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP