Duty ratio correcting circuit

Abstract

The invention belongs to the field of the signal processing technology, and discloses a duty ratio correcting circuit. The duty ratio correcting circuit comprises an input buffer, a duty ratio regulating circuit, a first-level CML-CMOS converting circuit and a duty ratio comparison circuit, wherein the input buffer is used for receiving a differential signal clka and a differential signal clkb, achieves initial adjustment of the duty ratio of the differential signals by setting a common mode level, and outputs a signal outla and a signal outlb, the duty ratio regulating circuit receives the signal outla and the signal outlb and outputs a signal out2a and a signal out2b, the first-level CML-CMOS converting circuit receives the signal out2a and the signal out2b, amplifies and rectifies the signal out2a and the signal out2b, and outputs a signal out3a and a signal out3b, and the duty ratio comparison circuit receives the signal out3a and the signal out3b, carries out amplification and integration on errors of the duty ratio, outputs a differential control voltage Vc+ and a differential control voltage Vc-, and feeds back the differential control voltage Vc+ and the differential control voltage Vc- to control the duty ratio regulating circuit. The duty ratio regulating circuit comprises a differential amplifier circuit and a compensation regulating unit, wherein the differential amplifier circuit amplifies the signal outla and the signal outlb, regulates the duty ratio, and outputs the regulated duty ratio to a next-level circuit, and the compensation regulating unit receives and feeds back the differential control voltages, outputs current compensation, regulates and outputs the common mode level of the signal out2a and the signal out2b and achieves feedback regulation of the duty ratio. The duty ratio correcting circuit improves correcting accuracy and efficiency.

Description

technical field [0001] The invention relates to the technical field of signal processing, in particular to a duty ratio correction circuit. Background technique [0002] With the wide application and continuous development of modern high technologies such as wireless communication, satellite positioning, remote control and telemetry technology, and precision guidance, differential signals, as important signal carriers, participate in many signal transmission systems. In addition to the traditional clock jitter, the performance of the differential signal, the duty cycle of the clock has increasingly become a key factor affecting the performance of high-speed integrated circuits. [0003] At present, commonly used duty ratio adjustment circuits can be roughly divided into two types: digital and analog. In comparison, the digital duty cycle adjustment circuit requires a complex control logic unit due to the need for matching between delay lines, and its correction accuracy is ...

AI Technical Summary

Problems solved by technology

In comparison, the digital duty cycle adjustment circuit requires a complex control logic unit due to the need for matching between delay lines, and its correction accuracy is discrete, so that accurate correction results cannot be obtained, and most digital adjustment circuits use drivers and The circuit structure such as a counter is realized, which makes the operating frequency of the whole system not too high, thereby limiting its application in high-frequency systems; the traditional analog correction circuit uses switched capacitors, which reduces the correction accuracy due to charge leakage and other reasons, and Also limits the operating frequency

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