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Three-input general logic gate circuit

A logic gate circuit and three-input technology, applied to logic circuits with logic functions, etc., can solve the problems of slow switching speed, high power consumption, and large volume, and achieve the effect of high switching speed and low power consumption

Inactive Publication Date: 2015-01-07
ZHEJIANG UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Existing general-purpose logic gate circuits are usually composed of CMOS devices, and CMOS devices are used to form NAND gates and NOT gates. There are technical defects: large volume, high power consumption, and slow switching speed

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with the drawings.

[0021] Reference Figure 1 ~ Figure 5 , A three-input general logic gate circuit, the circuit includes a first two-input NAND gate U1, a second two-input NAND gate U4, a third two-input NAND gate U5, a first two-input NAND gate U2 and a second inverter Gate U3, the first two-input NAND gate U1, the second two-input NAND gate U4, the third two-input NAND gate U5, the first inverter U2, and the second inverter U3 are all composed of single-electron transistors;

[0022] The first input terminal of the first two-input NAND gate U1 is connected to the input terminal of the first NOT gate U2 as the first input terminal V1 of the general logic gate circuit, and the second input terminal of the first two-input NAND gate U1 is used as The second input terminal V2 of the universal logic gate circuit, the output terminal of the first two-input NAND gate U1 and the first input terminal of the thi...

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Abstract

The invention discloses a three-input general logic gate circuit, which comprises a first two-input NAND gate U1, a second two-input NAND gate U4, a third two-input NAND gate U5, a first NOT gate U2 and a second NOT gate U3, wherein each gate circuit is formed by a single electron transistor; the first input end of the first two-input NAND gate U1 is connected to the input end of the first NOT gate U2, and the output end of the first two-input NAND gate U1 is connected to the first input end of the third two-input NAND gate U5; the output end of the first NOT gate U2 is connected to the first input end of the second two-input NAND gate U4; the input end of the second NOT gate U3 is taken as an input end V3 of the general logic gate circuit, and the output end of the second NOT gate U3 is connected to the second input end of the second two-input NAND gate U4; the output end of the second two-input NAND gate U4 is connected to the second input end of the third two-input NAND gate U5. The three-input general logic gate circuit has the advantages of nanometer ultra-small volume, ultra-low power consumption and extremely-high switching speed.

Description

Technical field [0001] The invention relates to the field of nanoelectronic technology, in particular to a general logic gate circuit. Background technique [0002] Integrated circuit technology has made amazing progress in the past 50 years, but power consumption and interconnection issues will make the feature size of traditional CMOS (Complementary Metal Oxide Semiconductor) devices shrink to their physical limits. When the feature size is reduced from the micron level to the nano level, quantum effects will dominate and may cause the device to fail. Therefore, while exploring the breakthrough of the physical limit of microelectronics, researchers have proposed the use of single electron transistors (SET, Single Electron Transistor). To replace the CMOS device research program, in order to develop new Very Large Scale Integration (VLSI, Very Large Scale Integration) technology. [0003] As a strong competitor of a new generation of nanoelectronic devices, SET requires only a fe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/20
Inventor 应时彦肖林荣张楠楠陈杰
Owner ZHEJIANG UNIV OF TECH
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