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Semiconductor device and manufacturing method thereof

A semiconductor and conductive type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as component damage, and achieve the effects of improved short-circuit resistance, reduced saturation current value, and low contact resistance

Active Publication Date: 2017-03-08
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this state, a drain current that is several times to several tens of times the rated current is induced in the component, and if there is no proper protection function, the component will be damaged

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0062] figure 1 It is a diagram schematically showing the upper surface structure of the silicon carbide MOSFET as a semiconductor device of the first embodiment. In addition figure 2 It is a diagram showing the structure of the outermost surface of the semiconductor layer of the semiconductor device. That is, the semiconductor device is figure 2 Formed on top of the semiconductor layer shown figure 1 It is composed of the elements shown.

[0063] Such as figure 1 In that way, the source pad (source electrode) 41, the gate wiring 44, and the gate pad 45 are formed on the upper surface of the chip 5 of the semiconductor device. The gate pad 45 is arranged near the center of one side of the chip 5. The gate wiring 44 is connected to the gate pad 45 and is formed so as to surround the source pad 41.

[0064] by figure 2 The area 7 surrounded by the dashed line is the active area 7 in which a plurality of unit cells 10 in which MOSFETs are arranged in parallel, and the source pad ...

Embodiment approach 2

[0146] In the first embodiment, the ion implantation for forming the source contact region 12a and the source extension region 12b and the ion implantation for forming the source resistance control region 15a are performed in different steps, but in the second embodiment , Proposed a technology of performing these processes in one ion implantation process.

[0147] Figure 21 It is a figure for demonstrating the manufacturing method of the silicon carbide MOSFET which is a semiconductor device of Embodiment 2. In this embodiment, it will be used in embodiment 1 Picture 11 The implantation mask 101a formed on the formation region of the source resistance control region 15a in the process shown in the description is as Figure 21 That replaces it with an implantation mask 101b with a thin thickness. The thickness of the implantation mask 101b is set to such a thickness that a part of the impurity penetrates during ion implantation of the impurity of the first conductivity type for...

Embodiment approach 3

[0161] In Embodiment 3, the following technique is proposed: using only one photoengraving process to form an implantation mask for forming the source contact region 12a and source extension region 12b, and an implantation mask for forming the well region 20 .

[0162] In Embodiment 3, after the source extension region 12b and the source contact region 12a are formed, the implantation mask used at that time is subjected to a cutting process, thereby processing it into a mask for forming the well region 20. Therefore, in this embodiment, the formation of the well region 20 is performed after the formation of the source contact region 12a and the source extension region 12b.

[0163] Figure 29 as well as Figure 30 It is a figure which shows the formation process of the well region 20, the source contact region 12a, and the source extension region 12b in this embodiment. Before the formation of the well region 20, such as Figure 29 In this way, the implantation masks 100d, 100dN o...

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Abstract

The source region (12) of the MOSFET includes a source contact region (12a) connected to the source pad (41), a source extension region (12b) adjacent to the channel region of the well region (20), and a The source resistance control region (15a) between the source extension region (12b) and the source contact region (12a) has an impurity concentration different from that of the source extension region (12b) and the source contact region (12a). These three regions are connected in series between the source pad (41) and the channel region of the well region (20).

Description

Technical field [0001] The invention relates to a structure of a semiconductor device and a manufacturing method thereof. Background technique [0002] Semiconductor elements based on silicon carbide (SiC) semiconductors are attracting attention as devices capable of achieving high withstand voltage and low loss. Especially for metal-oxide-semiconductor-field-effect-transistor (MOSFET) combined with a metal / insulator / semiconductor, high reliability is required from the viewpoint of application to power electronics. [0003] For example, when such a semiconductor element is applied to an inverter circuit and the like to operate an inductive load or a resistive load, the load short circuit such as an arm short circuit occurs. If the drain of the conductive element is applied as the power supply voltage The high voltage becomes a state where a large current flows in the element. In this state, a drain current of several to several tens of times the rated current is induced in the el...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/06H01L29/12H01L29/739
CPCH01L21/046H01L29/0619H01L29/1608H01L29/66068H01L29/7827H01L29/66893H01L29/8083H01L29/7813H01L29/0615H01L29/086H01L29/1095H01L29/7802H01L29/0696H01L29/7811H01L29/1033H01L29/42356H01L29/7836
Inventor 三浦成久日野史郎古川彰彦阿部雄次中田修平今泉昌之香川泰宏
Owner MITSUBISHI ELECTRIC CORP