Manufacturing method of semiconductor device

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of load effect, etching stop, loss of inter-layer dielectric layer, etc., and achieve good structure, The effect of simplifying the etching process
CN104347485AActive Publication Date: 2015-02-11SEMICON MFG INT (SHANGHAI) CORP
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Patent Information

Authority / Receiving Office
CN ยท China
Patent Type
Applications(China)
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2015-02-11

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Abstract

The invention provides a manufacturing method of a semiconductor device. The manufacturing method comprises the following steps: providing a semiconductor substrate, wherein a gate electrode and a side wall structure are formed on the semiconductor substrate, and a self-aligned metal silicide is formed on a source / drain region on the two sides of the gate electrode and the side wall structure; forming a first interlayer dielectric layer, a covering layer and a patterned photoresist layer on the semiconductor substrate in sequence; etching the covering layer and the first interlayer dielectric layer in sequence according to the patterned photoresist layer to expose a contact hole of the self-aligned metal silicide; filling metal in the contact hole; removing excess metal by using a chemical mechanical polishing process, wherein the loss of the first interlayer dielectric layer is not caused in the process of forming the contact hole through etching and in the metal chemical mechanical polishing process. According to the manufacturing process, the etching process can be simplified, the contact hole of a good structure is formed, and the formed contact hole meets the requirements of an integrated circuit.
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Description

technical field

[0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming a contact hole. Background technique

[0002] As the manufacture of integrated circuits develops toward ultra-large-scale integrated circuits (ULSI), the internal circuit density is increasing, and the number of components contained is increasing and decreasing, making the surface of the wafer unable to provide enough area to make the required interconnection lines. . Therefore, in order to meet the increased demand for interconnection lines after component shrinkage, the design of multilayer metal interconnection lines with more than two layers has become a necessary method for VLSI technology. At present, the conduction between different metal layers is achieved by digging an opening in the insulating layer between the two metal layers and filling it with a conductive material to form a contact hole structure that conducts the two metal layers. The...

Claims

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