High-speed ADC (Analog to Digital Converter) sampled data receiving and buffering method and system based on FPGA (Field Programmable Gate Array)
A sampling data and data technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of inability to record data before triggering, low sampling data storage speed, short recording time, etc., and achieve fast speed, easy processing, and control simple effect
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[0066] In order to make the method and technical solution of the present invention intuitive and easy to understand, the present invention will be further described with reference to the accompanying drawings in combination with the following specific embodiments.
[0067] The present invention provides an FPGA-based method and system for receiving and buffering high-speed ADC sampling data. The system mainly includes the following components: a data receiving delay unit U1, a data reduction unit U2, a clock receiving delay unit U3, a clock processing unit U4, Data combination storage unit U5, control unit U6, see structure composition figure 1 .
[0068] Among them, the data reception delay unit U1 realizes the data reception and delay adjustment; the data reduction unit U2 realizes the serial-to-parallel conversion, stretching and speed reduction of the data signal; the clock reception delay unit U3 realizes the clock reception, and the clock is coarsely delayed Time adjustment c...
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