High-speed ADC (Analog to Digital Converter) sampled data receiving and buffering method and system based on FPGA (Field Programmable Gate Array)

A sampling data and data technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of inability to record data before triggering, low sampling data storage speed, short recording time, etc., and achieve fast speed, easy processing, and control simple effect

CN104407998AActive Publication Date: 2015-03-11NORTHWEST INST OF NUCLEAR TECH
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2015-03-11

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Abstract

The invention provides a high-speed ADC (Analog to Digital Converter) sampled data receiving and buffering method and system based on an FPGA (Field Programmable Gate Array). The system mainly comprises a data receiving delay unit, a data speed-down unit, a clock receiving delay unit, a clock processing unit, a data combination storage unit and a control unit. Inside the FPGA, the data speed-down unit is used for lowering the speed of a data signal, a clock signal uses double-edge latch data, and the data delay unit is used for performing delay adjustment on a plurality of pairs of data signals, so that simultaneous hop of the pairs of data signals is ensured; the hop edge of the clock signal is positioned in the center of the data signal; the data combination unit is used for combining and arranging widened and slowed-down data to recover practical waveform data; the practical waveform data is stored in the data storage unit. By adopting the method and the system, a plurality of paths of data signals and clock signals accompanying the data can be received simultaneously, and the functions of circular storage, pre-trigger recording, sequential read-out and the like of the data signal are realized.
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Description

technical field

[0001] The invention relates to a high-speed sampling data receiving and buffering method and system, based on a field programmable gate array FPGA platform and a high-speed ADC sampling data receiving and buffering method and system developed by using VHDL hardware description language. The invention relates to the field of high-speed data collection and storage. The method and system can be widely used in high-speed data collection and recording, high-speed image collection, radar echo data collection, etc., to realize real-time loop storage and pre-trigger recording of multi-channel high-speed data signals And sequential readout, after expansion, it can realize functions such as real-time analysis of high-speed data. Background technique

[0002] As the application fields of the data acquisition system become more and more extensive, the requirements for its technical indicators are also getting higher and higher. Many applications require it to have a hig...

Examples

Embodiment Construction

[0066] In order to make the method and technical solution of the present invention intuitive and easy to understand, the present invention will be further described in conjunction with the following specific embodiments and with reference to the accompanying drawings.

[0067] The present invention provides a method and system for receiving and buffering high-speed ADC sampling data based on FPGA. The system mainly includes the following components: a data receiving delay unit U1, a data deceleration unit U2, a clock receiving delay unit U3, and a clock processing unit U4. Data combination storage unit U5, control unit U6, see structure composition figure 1 .

[0068] Among them, the data reception delay unit U1 realizes data reception and delay adjustment; the data deceleration unit U2 realizes the serial-to-parallel conversion of data signals, widening and deceleration; the clock reception delay unit U3 realizes the reception of the clock, and the coarse delay Timing adjust...