Eight-tube storage subarray structure with bit interleaving function

Abstract

The invention belongs to the technical field of integrated circuit storages, and particularly relates to an eight-tube storage subarray structure with a bit interleaving function. The cell structure comprises a m*1 subarray consisting of traditional single-ended eight-tube storage cells, a pair of PMOS (P-channel Metal Oxide Semiconductor) power sharing tubes respectively controlled by a whole bit line (WBL) and a complementary bit WBLB thereof and a pair of NMOS (N-channel Metal Oxide Semiconductor) discharge sharing tubes respectively controlled by a whole bit line (WBL) and a complementary bit WBLB thereof. The eight-tube storage subarray structure further comprises an eight-tube storage array consisting of n lists of m*1 subarrays; when write operation is carried out for a certain storage cell in the array, one column selection bit in the list becomes a high level, and the PMOS power sharing tubes controlled by the column selection bit line are disconnected, but the controlled NMOS discharge sharing tubes are open, so that data are written in the eight-tube storage cell through a ground passage formed by local bit lines and the discharge sharing tubes. The eight-tube storage subarray structure supports the bit interleaving function and also can eliminate semi-selective damage.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit memory, and in particular relates to a register file (Register File) and a static random access memory (Static Random Access Memory, SRAM) array structure. Background technique [0002] With the continuous development of process technology, the size of transistors is getting smaller and smaller, and the density and area of ​​chips are getting larger and larger, but the process deviation and device parameter mismatch are becoming more and more serious, and the power consumption of chips getting bigger. Both logic circuits and memories are susceptible to process variation and device parameter mismatch, especially for memories. [0003] The core of the traditional memory array is a 6-tube memory unit. In order to achieve high chip density, the 6-tube memory unit usually uses the smallest transistor size, which makes it more susceptible to interference caused by process changes than logic ...

AI Technical Summary

Problems solved by technology

Due to the differential write and single-end read operation of 8-tube storage, it cannot adopt the column selection structure. Therefore, in some high-density SRAMs, 8-tube storage units cannot be used.

The present invention proposes an 8-pipe storage unit sub-array structure supporting bit interleaving, which effectively solves the disadvantage that the 8-pipe storage unit cannot support the column selection structure

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