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Packaging structure and semiconductor process

A packaging structure and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of reduced mechanical strength of sealing glue, short circuit, increased material cost, etc.

Active Publication Date: 2018-08-03
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In the known packaging structure, several electrical connection elements are used to electrically connect the two substrates, and in order to maintain the distance between the two substrates, it is necessary to use high structural strength electrical connection elements (such as: copper) to support between the two substrates , resulting in an increase in material cost
Moreover, if the distance between the die on the lower substrate and the upper substrate is too small, the sealant is difficult to flow in, causing air or gaps in the space between the die on the lower substrate and the upper substrate, which may cause product defects, for example, because the sealant is between the die and the upper substrate. The uneven distribution between the substrates causes the mechanical strength of the sealant to be greatly reduced, reducing the reliability of the sealant itself and the adhesive strength of the sealant to the die or the upper substrate
[0003] In addition, when using the B-stage adhesive material as the cladding material, when pressing the upper substrate on the cladding material, since the B-stage adhesive material has not been fully cured, the distance between the crystal grains of the lower substrate and the upper substrate It is difficult to control. If the distance is too large, the electrical connection elements will not be able to contact the electrical contacts, which will cause an electrical short circuit. If the distance is too small, the die may be damaged during the process of pressing the substrate, resulting in product failure. Yield drop

Method used

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  • Packaging structure and semiconductor process
  • Packaging structure and semiconductor process
  • Packaging structure and semiconductor process

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Embodiment Construction

[0014] refer to figure 1 , shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. The packaging structure 10 includes: a first substrate 11 , a second substrate 12 , a chip 13 , several electrical connection elements 14 , at least one spacer element (spacerelement) 15 and a sealant 16 . The first substrate 11 has a first surface 111 and a plurality of first conductive contacts 112 , wherein the first conductive contacts 112 are exposed on the first surface 111 of the first substrate 11 . In one embodiment, the first substrate 11 further includes a first solder resist layer (not shown), the first surface 111 of the first substrate 11 is the surface of the first solder resist layer, and is exposed through the opening of the first solder resist layer The first conductive contact 112 . The first conductive contacts 112 can be conductive pads or conductive lines.

[0015] The second substrate 12 has a second surface 121 and a...

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Abstract

The present invention relates to a packaging structure and semiconductor technology. The packaging structure includes: a first substrate, a second substrate, a crystal grain, several electrical connection elements, at least one spacer element and sealant. The crystal grain is located between the first substrate and the second substrate, and the at least one spacing element is disposed between the crystal grain and the second substrate, and contacts the crystal grain and the second substrate. The electrical connection element is electrically connected to the first substrate and the second substrate. The at least one spacing element is used to support the second substrate, so that there is a set distance between the first substrate and the second substrate, and the electrical connection elements do not need to use high-strength materials to save material costs. And the at least one spacer element can control the distance and the space between the crystal grain and the second substrate, so that the sealant can flow into the space smoothly without generating air or voids in the space, which can improve the product yield.

Description

technical field [0001] The invention relates to a packaging structure and a semiconductor process. Background technique [0002] In the known packaging structure, several electrical connection elements are used to electrically connect the two substrates, and in order to maintain the distance between the two substrates, it is necessary to use high structural strength electrical connection elements (such as: copper) to support between the two substrates , resulting in increased material costs. Moreover, if the distance between the die of the lower substrate and the upper substrate is too small, the sealant is difficult to flow in, causing air or gaps in the space between the die of the lower substrate and the upper substrate, which may cause product defects, for example, because the sealant is between the die and the upper substrate. The uneven distribution between the substrates results in a significant reduction in the mechanical strength of the sealant, reducing the reliab...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/603H01L23/488
CPCH01L2224/16225H01L2224/17H01L2224/1718H01L2224/32225H01L2224/73204H01L2924/00
Inventor 陈勇仁丁一权郑文吉
Owner ADVANCED SEMICON ENG INC