Tightly coupled self-adaptive co-processing system supporting multi-core network processing framework

Abstract

The invention discloses a tightly coupled self-adaptive co-processing system supporting a multi-core network processing framework. The tightly coupled self-adaptive co-processing system includes a DAHM (Direct Access High-Speed Memory) which is a two-port SRAM (Static Random Access Memory) and is a primary data memory of a CPU for direction providing operand for the CPU; a DAMTCM (Downstream Adaptive Message Transmission Co-processing Module), for transmitting data between network interface controller and each one of multiple cores, wherein the DAMTCM directly accesses the DAHM; an UAHACM (Upstream Adaptive Hardware Acceleration Co-processing Module), for accelerating message process inside the multiple cores, wherein the UAHACM direct accesses the DAHM; an interpolation transmission arbitration module, positioned between the UAHACM and the DAHM, for being matched with the UAHACM to complete data transmission of the DAHM in an interpolating manner. The tightly coupled self-adaptive co-processing system has the advantages of being flexible and easy to program, capable of flexibly switching execution of hardware and wide in application range.

Description

technical field [0001] The invention mainly relates to the field of network packet processing-oriented multi-core network processor architecture, in particular to a tightly coupled adaptive co-processing system for supporting multi-core network processing architecture. Background technique [0002] The progress of network processing capability largely depends on the progress of hardware technology. At present, with the increasing complexity of network processing applications, the continuous growth of throughput and the continuous evolution of routing protocols, the performance requirements of network processing hardware are getting higher and higher. For network applications, network processing hardware has evolved from a general-purpose CPU architecture to an ASIC directly implemented by hardware, to an NP architecture that takes into account both flexibility and high performance, and then to a multi-core architecture. Pursue. For this reason, network processing hardware ...

AI Technical Summary

Problems solved by technology

[0004] However, the existing traditional structure also has the following disadvantages: firstly, the large memory access competition overhead, hardware DMA and thread memory access competition increases the memory access delay and reduces performance; secondly, the coprocessor synchronization overhead is relatively large , the coprocessor leads to frequent thread switching, and the cost of switching between threads is relatively high

Images