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Low on resistance LDMOS structure and manufacturing method thereof

A technology of low on-resistance and manufacturing method, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problem of inability to achieve low on-resistance LDMOS, LDMOS withstand voltage and on-resistance can not be optimized, etc. problem, achieve the effect of optimizing depth and angle, and improving on-resistance

Inactive Publication Date: 2015-04-22
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Simulation and actual silicon results show that the Idlin (linear region current) on the conductive path of LDMOS is greatly affected by this layer of STI, but due to the limitation of STI depth and etching angle, the withstand voltage and on-resistance of LDMOS cannot Do optimization, so it is impossible to achieve low on-resistance LDMOS

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  • Low on resistance LDMOS structure and manufacturing method thereof
  • Low on resistance LDMOS structure and manufacturing method thereof
  • Low on resistance LDMOS structure and manufacturing method thereof

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Embodiment Construction

[0017] In order to have a more specific understanding of the technical content, characteristics and effects of the present invention, now in conjunction with the accompanying drawings, the details are as follows:

[0018] The structure of the low on-resistance LDMOS of the present invention is as follows figure 1 As shown in Fig. 1 , STIs with conventional depths (namely STI 1) are used on both sides of the drift region, and ultra-shallow STIs with a depth significantly shallower than conventional STIs (namely STI 2) are used in the drift region.

[0019] Before making the LDMOS with STI structure of the present invention, the present invention first simulates the depth and angle of STI2 for 30V LDMOS.

[0020] STI2 depth simulation results are shown in Table 1 and figure 2 , 3 Shown:

[0021] Table 1 STI2 depth simulation results

[0022]

[0023] When the depth of STI2 is at Between the time, the breakdown voltage is basically unchanged, and the impact ionization d...

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Abstract

The invention discloses a low on resistance LDMOS structure. An ultra-shallow trench isolation structure is adopted in a drift region of the structure, and conventional shallow trench isolation structures are adopted in the two sides of the drift region. The invention further discloses a manufacturing method of the low on resistance LDMOS structure. The manufacturing method of the low on resistance LDMOS structure includes the forming steps that firstly, an active region is shielded by a mask, photo-etching is conducted, and conventional STI trenches are formed in the two sides of the drift region; secondly, photo-etching is conducted, and an ultra-shallow STI trench is formed in the drift region; thirdly, silicon dioxide is deposited in the trenches, chemical mechanical grinding is conducted, and conventional STI and ultra-shallow STI are formed. The ultra-shallow STI layer is introduced in the LDMOS structure to serve as an LDMOS drift region field plate medium, the etching depth and the etching angle are optimized, and then the voltage withstanding performance and the on resistance performance of an LDMOS are greatly improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to the structure and manufacturing method of LDMOS with low on-resistance. Background technique [0002] In the 0.18μm BCD process, conventional STI (Shallow Trench Isolation) is used as the field plate dielectric in the drift region of LDMOS (Laterally Diffused Metal Oxide Semiconductor), such as figure 1 shown. [0003] The depth of STI used as isolation is generally about The angle is about 80 degrees. Simulation and actual silicon results show that the Idlin (linear region current) on the conductive path of LDMOS is greatly affected by this layer of STI, but due to the limitation of STI depth and etching angle, the withstand voltage and on-resistance of LDMOS cannot It is optimized, so it is impossible to realize LDMOS with low on-resistance. Contents of the invention [0004] One of the technical problems to be solved by the present invention...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/265H01L29/78H01L29/06
CPCH01L29/7835H01L29/0653H01L29/66477H01L21/265H01L29/407H01L29/7816
Inventor 邢军军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP