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Fan-out PoP packaging structure and manufacturing method thereof

A technology of packaging structure and packaging body, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc.

Inactive Publication Date: 2015-04-22
HUATIAN TECH XIAN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention proposes a packaging structure and manufacturing method for the three-dimensional PoP packaging technology to solve the packaging density and cost problems existing in the existing PoP packaging technology

Method used

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  • Fan-out PoP packaging structure and manufacturing method thereof
  • Fan-out PoP packaging structure and manufacturing method thereof
  • Fan-out PoP packaging structure and manufacturing method thereof

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Embodiment Construction

[0036] In order to make the purpose, technical solution and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0037] Such as Figure 8As shown, a fan-out PoP packaging structure, the structure is composed of a lower package body 50 and an upper package body; the lower package body 50 includes a first metal bump structure 2, a first IC chip 3, a bonding Pad 4, first molding compound 6, rewiring metal wiring layer 7, first metal layer 8, dielectric material layer 9, second metal layer 10 and first solder ball 11; the first IC chip 3 has There are bonding pads 4, the second metal layer 10 is on the first metal bump structure 2, the first molding compound 6 surrounds the first IC chip 3 and the first metal bump structure 2, the sum of the first IC chip 3 The surface of the first metal bump structure 2 in the same direction is exposed; ...

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Abstract

The invention discloses a fan-out PoP packaging structure and a manufacturing method of the fan-out PoP packaging structure. Fan-out PoP packaging is formed by stacking an upper packaging body and a lower packaging body. The lower packaging body comprises first metal protrusion structures, first IC chips, bonding bonding pads, first molding compounds, rewiring metal wiring layers, first metal layers, a dielectric material layer, second metal layers and first solder balls. The bonding bonding pads of the first IC chip are connected with the rewiring metal wiring layers, molding compound through holes are formed by the first metal protrusion structures, and three-dimensional integrated interconnection between the upper packing body and the lower packaging body and the outer structure is achieved through the molding compound through holes. The manufacturing method of the packaging structure mainly comprises the steps that the first metal protrusion structures are manufactured on the upper surface of a first substrate, core mounting and plastic packaging are carried out, the rewiring metal wiring layers are manufactured, the lower surface of the first substrate is thinned, and the lower packaging body is formed through a ball planting and backflow process. A BGA packaging body and other packaging bodies are directly attached to the upper portion of the lower packaging body to be adopted as the upper packaging body, or core mounting, lead bonding and a plastic packaging process are arranged above the lower packaging body to from the upper packaging body, and the PoP packaging strcure is formed. The packaging density and cost problem of an existing PoP packaging technology is solved well.

Description

technical field [0001] The invention relates to the field of microelectronic packaging technology and three-dimensional integration technology, in particular to a three-dimensional PoP packaging technology and a manufacturing method thereof. Background technique [0002] With the continuous development of electronic packaging products in the direction of high density, multi-function, low power consumption, and miniaturization, the system-in-package (SiP) using three-dimensional integration technology has achieved rapid development. The Through Silicon Via (TSV) technology solution is the optimal solution for realizing 3D integration technology due to its characteristics of the highest stacking density, the smallest size, greatly improved chip speed and reduced power consumption. However, the manufacturing difficulty, process cost, finished product yield, reliability and other issues faced by TSV technology are also extremely prominent. The existing mature three-dimensional ...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L21/60
CPCH01L2224/73267H01L2224/92244H01L2225/1035H01L2225/1058H01L2225/1094H01L2924/15311H01L2924/18162H01L2224/04105H01L2224/12105H01L2224/19H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/48095H01L2224/48227H01L2224/48235H01L2224/73265H01L2924/00014H01L2924/00
Inventor 夏国峰于大全
Owner HUATIAN TECH XIAN