ESD (Electro-Static discharge) electrostatic protection structure for IO Pad

Abstract

The invention provides an ESD (Electro-Static discharge) electrostatic protection structure for an IO Pad. The structure comprises a substrate, two P type transistors, four N type transistors, an isolating resistor, two PAD channels and an N type well region. The structure adopts a non-ESD device to form a protection device, and adopts finger-shaped MOS tube units connected in parallel to form MOS tube parallel groups; a plurality of the MOS tube parallel groups are distributed side by side to form a large-sized electrostatic protection MOS device; a double-PAD channel adopted for layout planning and the double-PAD channel, an ESD protection N type MOS device region, and a P type MOS device are distributed at intervals. Compared with an ESD electrostatic protection structure for the IO Pad, provided by a technology producer, the ESD electrostatic protection structure for the IO Pad, provided by the invention, has the benefits that the process is simplified, other process designs are adopted in a compatible manner, so that equivalent electrostatic protection performance is achieved, and at the same time the electrostatic protection device is smaller in size, lower in cost, and is more convenient for people to improve the electrostatic protection device for antistatic ability improvement.

Description

technical field [0001] The invention belongs to the technical field of ESD electrostatic protection in integrated circuits, and in particular relates to an ESD electrostatic protection circuit structure of an IO Pad (input and output pin). Background technique [0002] Electrostatic Discharge (ESD) is the main factor that causes most electronic components or electronic systems to be damaged by excessive electrical stress. This damage can cause a permanent damage to the semiconductor components, affecting the circuit function of the integrated circuit. About 30% to 40% of the electrical failures of integrated circuit products are related to ESD electrostatic shocks. With the continuous development of CMOS technology, the feature size of integrated circuits is gradually reduced. When it comes to submicron and deep submicron technology, the gate length, gate oxide layer thickness, junction depth, and epitaxial layer thickness of the device are all reduced accordingly, making ...

AI Technical Summary

Problems solved by technology

Existing chips generally adopt the IO Pad electrostatic protection structure provided by the process manufacturer. The ESD protection devices are composed of specially designed ESD Device devices. The specific process flow, fixed layout structure and fixed size occupy a large area on the layout. , is one of the main reasons for the large layout area of ​​the IO Pad, resulting in high cost; at the same time, non-standard MOS device design is not easy to carry out compatible design of other processes, and it is not easy to improve the anti-static ability of ESD devices

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