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High-speed low-power-consumption multi-threshold-value asynchronous resizing reset retaining D-type trigger

A set reset, low power consumption technology, applied in the direction of pulse generation, electrical components, electric pulse generation, etc., can solve the problems of increasing circuit design complexity, consuming energy, increasing circuit area, etc.

Active Publication Date: 2015-05-13
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although it can reduce a certain power consumption, the tube itself will consume a certain amount of energy, and will increase the area of ​​the circuit and increase the complexity of the circuit design.

Method used

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  • High-speed low-power-consumption multi-threshold-value asynchronous resizing reset retaining D-type trigger
  • High-speed low-power-consumption multi-threshold-value asynchronous resizing reset retaining D-type trigger
  • High-speed low-power-consumption multi-threshold-value asynchronous resizing reset retaining D-type trigger

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Embodiment Construction

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0042] Such as figure 1 As shown, the high-speed low-power multi-threshold asynchronous set-reset-hold D-type flip-flop of the present invention includes a low-power control circuit, a set control circuit, a selection control circuit, a master latch and a slave latch. The flip-flop of the present invention has seven inputs and two outputs. The seven input terminals are used to connect respectively: positive-phase clock input signal clk, negative-phase clock input signal nclk, low-power control input signal slp, select data entry hold signal sel, asynchronous reset input signal r, asynchronous set input signal set and data input signal d; two output terminals are used for output: the first output signal q and the second output signal nq, the first output signal q and the second output signal nq are a pair of opposite data signals. in...

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Abstract

A high-speed low-power-consumption multi-threshold-value asynchronous resizing reset retaining D-type trigger comprises a low-power-consumption control circuit for receiving a low-power-consumption control input signal slp, conducting buffer processing on the low-power-consumption control input signal slp and then outputting signals, a resizing control circuit for receiving an asynchronous resizing input signal set, conducting buffer processing on the asynchronous resizing input signal set and then outputting the signals respectively, a selection control circuit for receiving selection data entering keeping signal sel, conducting buffer processing on the selection data entering keeping signal sel and then outputting signals respectively, a master latch for receiving a data input signal d, a normal phase input clock signal clk, a reverse phase input clock signal nclk, an asynchronous reset input signal r, the selection data entering keeping signal sel and signals sleep and nsleep, s and ns, latching the data input signal d and then outputting a signal qt, and a slave latch for conducting latching on the signal qt and then outputs the signals respectively. The high-speed low-power-consumption multi-threshold-value asynchronous resizing reset retaining D-type trigger has the advantages of being simple in structure, capable of improving transmission efficiency, reducing static leakage current and power consumption and the like.

Description

technical field [0001] The invention mainly relates to the field of large-scale integrated circuit design, in particular to a high-speed, low-power consumption multi-threshold asynchronous set-reset-hold D-type flip-flop. Background technique [0002] With the continuous improvement of process technology, VLSI design has entered the deep submicron stage. The reduction of the feature size will inevitably lead to the decrease of the threshold voltage of the MOS device, so that the leakage current of the circuit increases exponentially with the reduction of the feature size, which directly causes the rapid increase of the leakage current power consumption of the circuit. Static power consumption caused by leakage current cannot be ignored. [0003] For systems operating in the GHz range, the power consumption reaches tens of watts, or even hundreds of watts. Excessive power consumption has brought a series of problems and has become an important obstacle to the development of...

Claims

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Application Information

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IPC IPC(8): H03K3/356H03K3/012
CPCH03K3/012H03K3/3562
Inventor 胡封林刘衡竹鲁建壮扈啸万江华孙书为陈小文陈胜刚雷元武许邦建亓磊刘蓉容高新军
Owner NAT UNIV OF DEFENSE TECH
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