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SRAM memory unit array, SRAM memory and control method thereof

A memory cell array and memory cell technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problems of unfavorable integrated circuit integration, chip size miniaturization, increase in the number of transistors, increase in the size of the memory cell array, etc., to achieve Improvement of static noise margin, size reduction, effect of size reduction

Active Publication Date: 2015-05-20
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the SRAM memory cell 200 of 8T structure improves stability, the number of transistors increases, and the size of the memory cell array increases accordingly, which is not conducive to the improvement of integrated circuit integration and the miniaturization of chip size

Method used

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  • SRAM memory unit array, SRAM memory and control method thereof
  • SRAM memory unit array, SRAM memory and control method thereof
  • SRAM memory unit array, SRAM memory and control method thereof

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Embodiment Construction

[0025] Next, the present invention will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0026] It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, whe...

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PUM

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Abstract

The invention provides an SRAM storage unit array, an SRAM memory, and a control method thereof. The SRAM storage unit array comprises a plurality of word line pair arranged along the row direction, wherein each word line pair comprises a write word line and a read word line; a bit line pair arranged along the row direction, wherein the bit line pair comprises a first bit line and a second bit line; a plurality of storage units arranged between the word line pairs and the bit line pair, wherein each storage unit is connected to the corresponding work line pair and bit line pair and comprises a read terminal; and a read unit, wherein the read unit comprises a read transistor and a read bit line, and the read bit line is connected to the read terminals of the plurality of storage units through the read transistor. The provided SRAM storage unit array reduces the transistor number and the stability is improved at the same time.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an SRAM memory cell array, an SRAM memory with the SRAM memory cell array and a control method for the SRAM memory. Background technique [0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important part of digital systems. SRAM (Static Random Access Memory) has become an indispensable and important part of on-chip memory due to its advantages of low power consumption and high speed. SRAM can hold data as long as it is powered, there is no need to constantly refresh it. [0003] The overall structure of SRAM can be divided into two parts: memory cell array and peripheral circuit. In SRAM, the storage unit is the most basic and important component. The number of memory cells included in the array and the stability of the memory cells are two important factors affecting the performance of the SRAM. The lar...

Claims

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Application Information

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IPC IPC(8): G11C11/413
CPCG11C11/419
Inventor 陈金明
Owner SEMICON MFG INT (SHANGHAI) CORP